VLSI Design of a High-Performance Multicontext MQ Arithmetic Coder

The MQ arithmetic coding, which is an adaptive arithmetic coding developing from Q coding, has become a major throughput bottleneck of JPEG2000 compression due to its inherent serial operations. To overcome the bottleneck, this brief proposes a high-performance hardware architecture of the multicont...

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Vydané v:IEEE transactions on very large scale integration (VLSI) systems Ročník 31; číslo 3; s. 396 - 400
Hlavní autori: Jing, Peng, Zhang, Wei, Yan, Long, Liu, Yanyan
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York IEEE 01.03.2023
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:
Arithmetic coding
Computer architecture
Context
Encoding
Figure of merit
FPGA
Hardware
Image coding
Integrated circuits
JPEG2000
MQ arithmetic coding
multicontext architecture
Power consumption
Registers
Symbols
Throughput
Transform coding
ISSN:1063-8210, 1557-9999
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Abstract The MQ arithmetic coding, which is an adaptive arithmetic coding developing from Q coding, has become a major throughput bottleneck of JPEG2000 compression due to its inherent serial operations. To overcome the bottleneck, this brief proposes a high-performance hardware architecture of the multicontext MQ coder. The proposed architecture is capable of concurrent coding for two adjacent more probable symbols (MPSs). Performance analysis results show that the proposed coder consumes 1.61 CXD pairs per cycle and achieves a throughput of 506.93 MSymbols/s under 0.5 bpp bit rate. The proposed architecture not only achieves high throughput, but also maintains both low hardware utilization and low power consumption. Compared with the state-of-the-art two-context coder, the figure of merit (FoM) is increased by 38%. Compared with the single-context coder, the power-delay product (PDP) is reduced by 49%.
AbstractList The MQ arithmetic coding, which is an adaptive arithmetic coding developing from Q coding, has become a major throughput bottleneck of JPEG2000 compression due to its inherent serial operations. To overcome the bottleneck, this brief proposes a high-performance hardware architecture of the multicontext MQ coder. The proposed architecture is capable of concurrent coding for two adjacent more probable symbols (MPSs). Performance analysis results show that the proposed coder consumes 1.61 CXD pairs per cycle and achieves a throughput of 506.93 MSymbols/s under 0.5 bpp bit rate. The proposed architecture not only achieves high throughput, but also maintains both low hardware utilization and low power consumption. Compared with the state-of-the-art two-context coder, the figure of merit (FoM) is increased by 38%. Compared with the single-context coder, the power-delay product (PDP) is reduced by 49%.
Author Yan, Long
Liu, Yanyan
Zhang, Wei
Jing, Peng
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10.1007/s11265-014-0945-5
10.14569/IJACSA.2017.080621
10.1007/s11265-011-0655-1
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10.1007/s11554-017-0666-7
10.1109/ICOSP.2010.5655377
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SubjectTerms Arithmetic coding
Computer architecture
Context
Encoding
Figure of merit
FPGA
Hardware
Image coding
Integrated circuits
JPEG2000
MQ arithmetic coding
multicontext architecture
Power consumption
Registers
Symbols
Throughput
Transform coding
Title VLSI Design of a High-Performance Multicontext MQ Arithmetic Coder
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https://www.proquest.com/docview/2778706855
Volume 31
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