High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic

Convolutional neural networks (CNNs) are widely used and have achieved great success in computer vision and speech processing applications. However, deploying the large-scale CNN model in the embedded system is subject to the constraints of computation and memory. An optimized block-floating-point (...

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Vydané v:	IEEE transactions on very large scale integration (VLSI) systems Ročník 27; číslo 8; s. 1874 - 1885
Hlavní autori:	Lian, Xiaocong, Liu, Zhenyu, Song, Zhourui, Dai, Jiwu, Zhou, Wei, Ji, Xiangyang
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York IEEE 01.08.2019 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Accelerators Artificial neural networks Block floating point (BFP) Computational modeling Computer memory Computer vision convolutional neural network (CNN) accelerator Embedded systems Feature maps Field programmable gate arrays field-programmable gate array (FPGA) Floating point arithmetic Hardware Mathematical model Memory management Neural networks Quantization (signal) Retraining Rounding Speech processing three-level parallel
ISSN:	1063-8210, 1557-9999
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