POLAR: A Pipelined/Overlapped FPGA-Based LSTM Accelerator

In this brief, a low resource utilization field-programmable gate array (FPGA)-based long short-term memory (LSTM) network architecture for accelerating the inference phase is presented. The architecture has low-power and high-speed features that are achieved through overlapping the timing of the op...

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Vydáno v:	IEEE transactions on very large scale integration (VLSI) systems Ročník 28; číslo 3; s. 838 - 842
Hlavní autoři:	Bank-Tavakoli, Erfan, Ghasemzadeh, Seyed Abolfazl, Kamal, Mehdi, Afzali-Kusha, Ali, Pedram, Massoud
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	New York IEEE 01.03.2020 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:	Computer architecture Field programmable gate arrays Field-programmable gate array (FPGA) Hardware high speed Logic gates long short-term memory (LSTM) accelerator low power low resource utilization Mapping Power demand Power efficiency Power management Resource management Resource utilization Timing
ISSN:	1063-8210, 1557-9999
On-line přístup:	Získat plný text
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