Core Transform Design in the High Efficiency Video Coding (HEVC) Standard

This paper describes the core transforms specified for the high efficiency video coding (HEVC) standard. Core transform matrices of various sizes from 4 × 4 to 32 × 32 were designed as finite precision approximations to the discrete cosine transform (DCT). Also, special care was taken to allow imple...

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Bibliographic Details
Published in:IEEE journal of selected topics in signal processing Vol. 7; no. 6; pp. 1029 - 1041
Main Authors: Budagavi, Madhukar, Fuldseth, Arild, Bjontegaard, Gisle, Sze, Vivienne, Sadafale, Mangesh
Format: Journal Article
Language:English
Published: New York IEEE 01.12.2013
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Algorithms
Data compression
Discrete cosine transform
Discrete cosine transforms
high efficiency video coding
transform design
Video coding
ISSN:1932-4553, 1941-0484
Online Access:Get full text
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Summary:This paper describes the core transforms specified for the high efficiency video coding (HEVC) standard. Core transform matrices of various sizes from 4 × 4 to 32 × 32 were designed as finite precision approximations to the discrete cosine transform (DCT). Also, special care was taken to allow implementation friendliness, including limited bit depth, preservation of symmetry properties, embedded structure and basis vectors having almost equal norm. The transform design has the following properties: 16 bit data representation before and after each transform stage (independent of the internal bit depth), 16 bit multipliers for all internal multiplications, no need for correction of different norms of basis vectors during quantization/de-quantization, all transform sizes above 4 × 4 can reuse arithmetic operations for smaller transform sizes, and implementations using either pure matrix multiplication or a combination of matrix multiplication and butterfly structures are possible. The transform design is friendly to parallel processing and can be efficiently implemented in software on SIMD processors and in hardware for high throughput processing.
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ISSN:1932-4553
1941-0484
DOI:10.1109/JSTSP.2013.2270429