Multisymbol Architecture of the Entropy Coder for H.265/HEVC Video Encoders

In video compression, throughputs of entropy encoders based on arithmetic coding are limited. This article presents the architecture of the entropy coder able to process in each clock cycle much more binary symbols than previous works. The architecture takes advantage of the multisymbol implementati...

Full description

Saved in:

Bibliographic Details
Published in:	IEEE transactions on very large scale integration (VLSI) systems Vol. 28; no. 12; pp. 2573 - 2583
Main Author:	Pastuszak, Grzegorz
Format:	Journal Article
Language:	English
Published:	New York IEEE 01.12.2020 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Arithmetic coding Binary arithmetic coding Coders Context Context modeling Data transmission Encoding Entropy Entropy coding Field programmable gate arrays field-programmable gate array (FPGA) H265/HEVC Mathematical analysis Multiplexing Streaming media Symbols Throughput UHDTV Video compression
ISSN:	1063-8210, 1557-9999
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!

Be the first to leave a comment!