Dual-Channel Multiplier for Piecewise-Polynomial Function Evaluation for Low-Power 3-D Graphics

A dual-channel multiplier (DCM) for energy efficient second-order piecewise-polynomial function evaluation for 3-D graphics applications is presented in this paper. The performance of the evaluation process is highly dependent on the design of the multiplication and squaring structure. A novel hardw...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems Vol. 27; no. 4; pp. 790 - 798
Main Authors: Ellaithy, Dina M., El-Moursy, Magdy A., Zaki, Amal, Zekry, Abdelhalim
Format: Journal Article
Language:English
Published: New York IEEE 01.04.2019
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
3-D graphics
Approximation algorithms
Channel multipliers
Clocks
Complexity
Computer architecture
Converters
Dual channel multiplier (DCM)
Energy conservation
graphical processing unit (GPU)
Graphics processing units
Hardware
low power
Multiplication
multiplier adder converter (MAC)
piecewuise-polynomial evaluation
Polynomials
Power consumption
Power demand
radix-4 squaring unit
Segmentation
Very large scale integration
ISSN:1063-8210, 1557-9999
Online Access:Get full text
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Summary:A dual-channel multiplier (DCM) for energy efficient second-order piecewise-polynomial function evaluation for 3-D graphics applications is presented in this paper. The performance of the evaluation process is highly dependent on the design of the multiplication and squaring structure. A novel hardware implementation for polynomial evaluation is presented. The proposed approach compensates the complex multipliers by using DCM which reduces the hardware complexity. The DCM scheme performs complex functions with power-efficient and area-efficient approach. The multiplier reduces the hardware computational effort in the piecewise polynomial approximation with uniform or nonuniform segmentation. For large operand input size, a multiplier adder converter and a dedicated radix-4 squaring unit are also proposed. These units achieve the least power consumption compared to previous approaches with large input word size. Comparison with general purpose multiplication has shown reduction in power, and delay by up to 36%, and 50%, respectively. The proposed technique exhibits up to 93% saving in power consumption compared to the current traditional schemes.
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ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2018.2889769