A Unified Hardware Design for Multiplication, Division, and Square Roots Using Binary Logarithms

Multiplication, division, and square root operations introduce significant challenges in digital signal processing (DSP) systems, traditionally requiring multiple operations that increase execution time and hardware complexity. This study presents a novel approach that leverages binary logarithms to...

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Vydané v:	Symmetry (Basel) Ročník 16; číslo 9; s. 1138
Hlavní autori:	Ngo, Dat, Han, Siyeon, Kang, Bongsoon
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	Basel MDPI AG 01.09.2024
Predmet:	Accuracy Algorithms Approximation Design standards Digital signal processing Digital signal processors Dividing (mathematics) Fourier transforms Hardware Logarithms Multiplication Multiplication & division Number systems Resource utilization Semiconductor industry Signal processing Subtraction United States
ISSN:	2073-8994, 2073-8994
On-line prístup:	Získať plný text
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