A Unified Hardware Design for Multiplication, Division, and Square Roots Using Binary Logarithms

Multiplication, division, and square root operations introduce significant challenges in digital signal processing (DSP) systems, traditionally requiring multiple operations that increase execution time and hardware complexity. This study presents a novel approach that leverages binary logarithms to...

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Vydáno v:Symmetry (Basel) Ročník 16; číslo 9; s. 1138
Hlavní autoři: Ngo, Dat, Han, Siyeon, Kang, Bongsoon
Médium: Journal Article
Jazyk:angličtina
Vydáno: Basel MDPI AG 01.09.2024
Témata:
Accuracy
Algorithms
Approximation
Design standards
Digital signal processing
Digital signal processors
Dividing (mathematics)
Fourier transforms
Hardware
Logarithms
Multiplication
Multiplication & division
Number systems
Resource utilization
Semiconductor industry
Signal processing
Subtraction
United States
ISSN:2073-8994, 2073-8994
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Abstract Multiplication, division, and square root operations introduce significant challenges in digital signal processing (DSP) systems, traditionally requiring multiple operations that increase execution time and hardware complexity. This study presents a novel approach that leverages binary logarithms to perform these operations using only addition, subtraction, and shifts, enabling a unified hardware implementation—a marked departure from conventional methods that handle these operations separately. The proposed design, involving logarithm and antilogarithm calculations, exhibits an algebraically symmetrical pattern that further optimizes the processing flow. Additionally, this study introduces innovative log-domain correction terms specifically designed to minimize computation errors—a critical improvement over existing methods that often struggle with precision. Compared to standard hardware implementations, the proposed design significantly reduces hardware resource utilization and power consumption while maintaining high operational frequency.
AbstractList Multiplication, division, and square root operations introduce significant challenges in digital signal processing (DSP) systems, traditionally requiring multiple operations that increase execution time and hardware complexity. This study presents a novel approach that leverages binary logarithms to perform these operations using only addition, subtraction, and shifts, enabling a unified hardware implementation—a marked departure from conventional methods that handle these operations separately. The proposed design, involving logarithm and antilogarithm calculations, exhibits an algebraically symmetrical pattern that further optimizes the processing flow. Additionally, this study introduces innovative log-domain correction terms specifically designed to minimize computation errors—a critical improvement over existing methods that often struggle with precision. Compared to standard hardware implementations, the proposed design significantly reduces hardware resource utilization and power consumption while maintaining high operational frequency.
Audience Academic
Author Han, Siyeon
Kang, Bongsoon
Ngo, Dat
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  fullname: Kang, Bongsoon
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SubjectTerms Accuracy
Algorithms
Approximation
Design standards
Digital signal processing
Digital signal processors
Dividing (mathematics)
Fourier transforms
Hardware
Logarithms
Multiplication
Multiplication & division
Number systems
Resource utilization
Semiconductor industry
Signal processing
Subtraction
Title A Unified Hardware Design for Multiplication, Division, and Square Roots Using Binary Logarithms
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