Koteshwara, S., Das, A., & Parhi, K. K. (2019). Architecture Optimization and Performance Comparison of Nonce-Misuse-Resistant Authenticated Encryption Algorithms. IEEE transactions on very large scale integration (VLSI) systems, 27(5), 1053-1066. https://doi.org/10.1109/TVLSI.2019.2894656
Chicago-Zitierstil (17. Ausg.)Koteshwara, Sandhya, Amitabh Das, und Keshab K. Parhi. "Architecture Optimization and Performance Comparison of Nonce-Misuse-Resistant Authenticated Encryption Algorithms." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27, no. 5 (2019): 1053-1066. https://doi.org/10.1109/TVLSI.2019.2894656.
MLA-Zitierstil (9. Ausg.)Koteshwara, Sandhya, et al. "Architecture Optimization and Performance Comparison of Nonce-Misuse-Resistant Authenticated Encryption Algorithms." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 5, 2019, pp. 1053-1066, https://doi.org/10.1109/TVLSI.2019.2894656.