An Efficient FPGA Implementation of Orthogonal Matching Pursuit With Square-Root-Free QR Decomposition

Compressive sensing (CS) is a novel signal processing technology to reconstruct the sparse signal at sub-Nyquist rate. Orthogonal matching pursuit (OMP) is one of the most widely used signal reconstruction algorithms. However, the least square problem (LSP) in OMP algorithm limits its performance. T...

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Vydáno v:IEEE transactions on very large scale integration (VLSI) systems Ročník 27; číslo 3; s. 611 - 623
Hlavní autoři: Ge, Xiang, Yang, Fan, Zhu, Hengliang, Zeng, Xuan, Zhou, Dian
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York IEEE 01.03.2019
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
Algorithms
Compressed sensing
Compressive sensing (CS)
Computation
Computer architecture
Decomposition
Field programmable gate arrays
field-programmable gate array (FPGA)
Hardware
Matching pursuit algorithms
Matrix decomposition
orthogonal matching pursuit (OMP)
QR decomposition (QRD)
Root matching
Schedules
Signal processing
Signal processing algorithms
Signal reconstruction
square root free (SRF)
State of the art
Workload
ISSN:1063-8210, 1557-9999
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Shrnutí:Compressive sensing (CS) is a novel signal processing technology to reconstruct the sparse signal at sub-Nyquist rate. Orthogonal matching pursuit (OMP) is one of the most widely used signal reconstruction algorithms. However, the least square problem (LSP) in OMP algorithm limits its performance. This paper presents a fast CS reconstruction algorithm implemented on field-programmable gate array (FPGA) using OMP. The proposed algorithm adopts an incremental QR decomposition (QRD) method to efficiently solve the LSP. The incremental QRD is further optimized to eliminate the square root operation to facilitate hardware implementation. The proposed architecture avoiding the complex square root unit mainly consists of some more basic computing units, where the computing process is broken down into several simple operations to map to the corresponding hardware for pipelining. The proposed implementation based on Xilinx Kintex-7 FPGA exploits the parallelism by a well-planned workload schedule and reaches an optimal tradeoff between the latency and frequency. The experimental results demonstrate that the proposed architecture can run at a frequency of 210 MHz with a reconstruction time of 238 <inline-formula> <tex-math notation="LaTeX">\mu \text{s} </tex-math></inline-formula> for 36-sparse 1024-length signal, which improves the signal reconstruction speed by <inline-formula> <tex-math notation="LaTeX">1.43\times </tex-math></inline-formula> compared to the state-of-the-art implementations.
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ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2018.2879884