APA (7th ed.) Citation

Nashimoto, S., Suzuki, D., Ueno, R., & Homma, N. (2021). Bypassing Isolated Execution on RISC-V using Side-Channel-Assisted Fault-Injection and Its Countermeasure. IACR transactions on cryptographic hardware and embedded systems, 2022(1), 28-68. https://doi.org/10.46586/tches.v2022.i1.28-68

Chicago Style (17th ed.) Citation

Nashimoto, Shoei, Daisuke Suzuki, Rei Ueno, and Naofumi Homma. "Bypassing Isolated Execution on RISC-V Using Side-Channel-Assisted Fault-Injection and Its Countermeasure." IACR Transactions on Cryptographic Hardware and Embedded Systems 2022, no. 1 (2021): 28-68. https://doi.org/10.46586/tches.v2022.i1.28-68.

MLA (9th ed.) Citation

Nashimoto, Shoei, et al. "Bypassing Isolated Execution on RISC-V Using Side-Channel-Assisted Fault-Injection and Its Countermeasure." IACR Transactions on Cryptographic Hardware and Embedded Systems, vol. 2022, no. 1, 2021, pp. 28-68, https://doi.org/10.46586/tches.v2022.i1.28-68.