DIMCA: An Area-Efficient Digital In-Memory Computing Macro Featuring Approximate Arithmetic Hardware in 28 nm

Recent SRAM-based in-memory computing (IMC) hardware demonstrates high energy efficiency and throughput for matrix-vector multiplication (MVM), the dominant kernel for deep neural networks (DNNs). Earlier IMC macros have employed analog-mixed-signal (AMS) arithmetic hardware. However, those so-calle...

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Bibliographic Details
Published in:	IEEE journal of solid-state circuits Vol. 59; no. 3; pp. 960 - 971
Main Authors:	Lin, Chuan-Tung, Wang, Dewei, Zhang, Bo, Chen, Gregory K., Knag, Phil C., Krishnamurthy, Ram Kumar, Seok, Mingoo
Format:	Journal Article
Language:	English
Published:	New York IEEE 01.03.2024 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Accuracy Approximate computing Approximation approximation-aware training Arithmetic Artificial neural networks Compressors Computation Deep learning Hardware In-memory computing in-memory computing (IMC) Integrated circuit modeling Mathematical analysis Multiplication neural network accelerators Static random access memory
ISSN:	0018-9200, 1558-173X
Online Access:	Get full text
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