Efficient 3-D Processor Array Reconfiguration Algorithms Based on Bucket Effect

With the progressive augmentation of the density of 3-D processor arrays, some processor elements (PEs) often fail due to overload or overheating during massively parallel computing operations. Therefore, it is necessary to take effective fault-tolerant technology to ensure the reliability of the sy...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems Jg. 43; H. 4; S. 1023 - 1036
Hauptverfasser:	Ding, Hao, He, Yanlong, Zhai, Zhongyi, Li, Zhi, Qian, Junyan, Zhao, Lingzhong
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.04.2024 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	3-D very large-scale integration (VLSI) array algorithm Algorithms Array processors Circuit faults Fault tolerance Fault tolerant systems Heuristic Integrated circuit interconnections interconnection length Iterative methods Logic arrays Lower bounds Microprocessors Overheating Parallel processing Power consumption Reconfiguration Reconstruction Redundancy Switches Three-dimensional displays
ISSN:	0278-0070, 1937-4151
Online-Zugang:	Volltext
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