NEST: A Quadruple-Node Upset Recovery Latch Design and Algorithm-Based Recovery Optimization

Multinode upset induced by radiation on integrated circuits has caused many circuit reliability issues. This article proposes a single-event quadruple-node upset (QNU) recovery latch (NEST), based on four circular feedback loops that are formed by 25 C-elements to realize high robustness. NEST achie...

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Vydáno v:IEEE transactions on aerospace and electronic systems Ročník 60; číslo 4; s. 4590 - 4600
Hlavní autoři: Huang, Zhengfeng, Sun, Liting, Wang, Xu, Liang, Huaguo, Lu, Yingchun, Yan, Aibin, Pan, Jun, Wen, Xiaoqing
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York IEEE 01.08.2024
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
Aerospace and electronic systems
Algorithms
Circuit reliability
Design optimization
Feedback loops
High impedance
Integrated circuits
Inverters
Latches
Logic gates
Nodes
Optimization
Optimization algorithm
Power demand
quadruple-node upset (QNU) recovery
Radiation hardening (electronics)
radiation hardening by design
Recovery
recovery rate
ISSN:0018-9251, 1557-9603
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Shrnutí:Multinode upset induced by radiation on integrated circuits has caused many circuit reliability issues. This article proposes a single-event quadruple-node upset (QNU) recovery latch (NEST), based on four circular feedback loops that are formed by 25 C-elements to realize high robustness. NEST achieves 29.02% reduction in power consumption compared to the latch design and algorithm-based verification protected against multiple-node upset (LDAVPM) latch and 51.44% reduction in setup time compared to the quadruple-node upset recoverable and high-impedance-state insensitive latch (QRHIL) latch. NEST also achieves a 99.29% QNU recovery rate. Furthermore, a high-speed, high-precision optimization algorithm for multinode upset recovery is also proposed and implemented. This algorithm achieves 99.84 reduction in simulation time for exhaustive fault injections having equivalent accuracy with high performance simulation program with integrated circuit emphasis (HSPICE).
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ISSN:0018-9251
1557-9603
DOI:10.1109/TAES.2024.3379962