Exploiting the Single-Symbol LLR Variation to Accelerate LDPC Decoding for 3-D NAND Flash Memory

Low-density parity-check (LDPC) codes have been widely adopted to guarantee data reliability in 3-D NAND flash memory. However, the iterative LDPC decoding algorithm leads to high decoding latency due to the iterative message transfer mechanism. Using a field-programmable gate array (FPGA) testbed,...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems Jg. 42; H. 12; S. 1
Hauptverfasser:	Li, Yingge, Han, Guojun, Liu, Chang, Zhang, Meng, Wu, Fei
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.12.2023 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	3-D NAND flash memory Algorithms binary channel Bit error rate Decoding Error analysis Error correcting codes Feedback Field programmable gate arrays Flash memories Flash memory (computers) Frames Iterative decoding LDPC Likelihood ratio raw bit error rate Reliability single-symbol LLR variation Symbols
ISSN:	0278-0070, 1937-4151
Online-Zugang:	Volltext
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