An Energy-Efficient Accelerator for Medical Image Reconstruction From Implicit Neural Representation

This work presents an energy-efficient accelerator for medical image reconstruction from implicit neural representation (INR). The accelerator implements an INR-based algorithm to deliver high-quality medical image reconstruction with arbitrary resolution from a compact implicit format. In particula...

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Vydáno v:IEEE transactions on circuits and systems. I, Regular papers Ročník 70; číslo 4; s. 1625 - 1638
Hlavní autoři: Rao, Chaolin, Wu, Qing, Zhou, Pingqiang, Yu, Jingyi, Zhang, Yuyao, Lou, Xin
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York IEEE 01.04.2023
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
accelerator
Algorithms
Biological neural networks
Central processing units
Computation
Computational modeling
Computer architecture
CPUs
Energy efficiency
energy-efficient
Field programmable gate arrays
Frames per second
Graphics processing units
Image coding
Image quality
Image reconstruction
Image resolution
implicit neural representation (INR)
Medical diagnostic imaging
Medical image reconstruction
Medical imaging
Performance evaluation
Power consumption
Representations
Three-dimensional displays
ISSN:1549-8328, 1558-0806
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Shrnutí:This work presents an energy-efficient accelerator for medical image reconstruction from implicit neural representation (INR). The accelerator implements an INR-based algorithm to deliver high-quality medical image reconstruction with arbitrary resolution from a compact implicit format. In particular, we propose a dedicated hardware architecture based on an optimized computation flow for the INR-based reconstruction algorithm, which co-designs data reuse and computation load. The proposed architecture takes in the coordinate of the intersection of three scans and outputs all the voxel intensities, minimizing the data movement between on-chip and off-chip. To validate the proposed accelerator, we build a proof-of-concept prototype demonstration system using field programmable gate array (FPGA). We also map our design to 40nm CMOS technology to measure the performance of the proposed accelerator. The implementation results show that, running at 400MHz, the proposed accelerator is capable of processing medical images with <inline-formula> <tex-math notation="LaTeX">256\times 256 </tex-math></inline-formula> resolution in real-time at 26.3 frames per second (FPS), with a power consumption of only 795 mW. Comparison results show that the performance, as well as the energy efficiency of the proposed accelerator, outperforms the central processing unit (CPU)-based and graphic processing unit (GPU)-based implementations.
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ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2022.3231863