Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9-14.3-GHz 85-fs-rms Jitter PLL

This article presents a wideband, low-jitter frequency synthesizer utilizing a dual-mode voltage-controlled oscillator (VCO). Mode imbalance in the dual-mode VCO is analyzed theoretically and compensated through the proposed symmetric figure-8 transformer and capacitor arrays. The compact mode-switc...

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Veröffentlicht in:IEEE journal of solid-state circuits Jg. 58; H. 8; S. 1 - 15
Hauptverfasser: Wang, Yizhuo, Shi, Jiahe, Xu, Hao, Ji, Shujiang, Mao, Yiyun, Zou, Tenghao, Tao, Jun, Min, Hao, Yan, Na
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.08.2023
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Algorithms
Arrays
Broadband
Capacitors
Circuits
Figure-8 transformer
Frequency ranges
frequency synthesizer
Frequency synthesizers
hierarchical optimization
low jitter
mode switching
Optimization
Oscillators
Phase locked loops
Phase noise
phase noise (PN)
phase-locked loop (PLL)
Power consumption
Switches
Transformers
Tuning
Vibration
Voltage controlled oscillators
voltage-controlled oscillator (VCO)
Wideband
ISSN:0018-9200, 1558-173X
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Zusammenfassung:This article presents a wideband, low-jitter frequency synthesizer utilizing a dual-mode voltage-controlled oscillator (VCO). Mode imbalance in the dual-mode VCO is analyzed theoretically and compensated through the proposed symmetric figure-8 transformer and capacitor arrays. The compact mode-switching circuitry fundamentally eliminates mode ambiguity in multi-mode autonomous circuits. A computer-aided algorithm based on sequential least-squares programming (SLSQP) and hierarchical optimization method is developed to automatically optimize the capacitor array in the wideband VCO. The implemented dual-mode VCO suppresses the phase noise (PN) difference across the operating frequency range, which further enables a sub-sampling phase-locked loop (SSPLL) to achieve near-minimum jitter across a wide frequency range without loop gain adaptation. Fabricated in a 40-nm CMOS process, the wideband SSPLL covers the frequency range of 7.9-14.3 GHz with 14.1-17.2-mW power consumption and occupies only 0.18-mm<inline-formula> <tex-math notation="LaTeX">^2</tex-math> </inline-formula> area. The SSPLL achieves better than <inline-formula> <tex-math notation="LaTeX">-</tex-math> </inline-formula>115-dBc/Hz in-band PN at a 10-GHz carrier. The rms jitter is less than 85 fs across the whole frequency range. The corresponding figure-of-merit tuning (FoM<inline-formula> <tex-math notation="LaTeX">_T</tex-math> </inline-formula>) is <inline-formula> <tex-math notation="LaTeX">-</tex-math> </inline-formula>247.1 to <inline-formula> <tex-math notation="LaTeX">-</tex-math> </inline-formula>248.1 dB.
Bibliographie:ObjectType-Article-1
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content type line 14
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2023.3242617