Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9-14.3-GHz 85-fs-rms Jitter PLL - Wang, Yizhuo; Shi, Jiahe; Xu, Hao; Ji, Shujiang; Mao, Yiyun; Zou, Tenghao; Tao, Jun; Min, Hao; Yan, Na (IEEE journal of solid-state circuits, 2023)
This article presents a wideband, low-jitter frequency synthesizer utilizing a dual-mode voltage-controlled oscillator (VCO). Mode imbalance in the dual-mode VCO is analyzed theoretically and compensated through the proposed symmetric figure-8 transformer and capacitor arrays. The compact mode-switching circuitry fundamentally eliminates mode ambiguity in multi-mode autonomous circuits. A computer-aided algorithm based on sequential least-squares programming (SLSQP) and hierarchical optimization method is developed to automatically optimize the capacitor array in the wideband VCO. The implemented dual-mode VCO suppresses the phase noise (PN) difference across the operating frequency range, which further enables a sub-sampling phase-locked loop (SSPLL) to achieve near-minimum jitter across a wide frequency range without loop gain adaptation. Fabricated in a 40-nm CMOS process, the wideband SSPLL covers the frequency range of 7.9-14.3 GHz with 14.1-17.2-mW power consumption and occupies only 0.18-mm ^2 area. The SSPLL achieves better than - 115-dBc/Hz in-band PN at a 10-GHz carrier. The rms jitter is less than 85 fs across the whole frequency range. The corresponding figure-of-merit tuning (FoM _T ) is - 247.1 to - 248.1 dB.