Sequential Circuits Synthesis for Rapid Single Flux Quantum Logic Based on Finite State Machine Decomposition

Rapid Single Flux Quantum (RSFQ) logic is a promising technology to supersede Complementary metal-oxidesemiconductor (CMOS) logic in some specialized areas due to providing ultra-fast and energy-efficient circuits. To realize a large-scale integration design, electronic design automation (EDA) tools...

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Veröffentlicht in:IEEE transactions on computer-aided design of integrated circuits and systems Jg. 42; H. 10; S. 1
Hauptverfasser: Yang, Shucheng, Gao, Xiaoping, Ren, Jie
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.10.2023
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Algorithms
Automata
Circuit design
Circuits
Clocks
CMOS
Decomposition
Electronic Design Automation
Feedback loops
Finite state machines
Flip-flops
Integrated circuit modeling
Logic gates
Logic synthesis
Logic SynthesisC Sequential Circuits
Rapid Single Flux Quantum Logic
Semiconductor device modeling
Sequential circuits
ISSN:0278-0070, 1937-4151
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Zusammenfassung:Rapid Single Flux Quantum (RSFQ) logic is a promising technology to supersede Complementary metal-oxidesemiconductor (CMOS) logic in some specialized areas due to providing ultra-fast and energy-efficient circuits. To realize a large-scale integration design, electronic design automation (EDA) tools specialized for RSFQ logic are required due to the divergences in logic type, timing constraints, and circuit structure compared with CMOS logic. Logic synthesis is crucial in converting behavioral circuit description into a circuit netlist, typically combining combinational and sequential circuit synthesis. For the RSFQ logic, the sequential circuit synthesis is challenging, especially for non-linear sequential blocks with feedback loops. Thus, this paper presents a sequential circuit synthesis algorithm based on finite state machine (FSM) decomposition, which ensures design functionality, lowers costs, and improves the RSFQ circuit performance. Additionally, we present the synthesis processes of the feedback logic and the 2-bit counter to demonstrate how the proposed algorithm operates, and ISCAS89 benchmark circuits reveal our method's ability to synthesize large-scale sequential circuits.
Bibliographie:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2023.3245542