High Throughput and Hardware Efficient Hybrid LDPC Decoder Using Bit-Serial Stochastic Updating

Hybrid low-density parity-check (LDPC) decoding combines conventional Belief-Propagation (BP) algorithm with stochastic decoding to achieve high performance and low complexity simultaneously. However, lossy and inefficient stochastic-to-binary (S2B) conversion brings extra performance degradation an...

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Bibliographic Details
Published in:	IEEE transactions on circuits and systems. I, Regular papers Vol. 70; no. 9; pp. 1 - 12
Main Authors:	Hu, Shuai, Han, Kaining, Zhu, Yubin, Shen, Guodong, Wang, Fujie, Hu, Jianhao
Format:	Journal Article
Language:	English
Published:	New York IEEE 01.09.2023 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Algorithms Codes Conversion Decoders Decoding EPON Error correcting codes fully correlated stochastic Hardware IEEE 802.3 Standard Iterative decoding LDPC code min-sum algorithm Nodes Performance degradation Performance enhancement probability tracer Stochastic processes Throughput
ISSN:	1549-8328, 1558-0806
Online Access:	Get full text
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