3-D In-Sensor Computing for Real-Time DVS Data Compression: 65-nm Hardware-Algorithm Co-Design

Traditional IO links are insufficient to transport high volume of image sensor data, under stringent power and latency constraints. To address this, we demonstrate a low latency, low power in-sensor computing architecture to compress the data from a 3D-stacked dynamic vision sensor (DVS). In this de...

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Vydané v:	IEEE solid-state circuits letters Ročník 7; s. 119 - 122
Hlavní autori:	Nair, Gopikrishnan R., Nalla, Pragnya S., Krishnan, Gokul, Anupreetham, Oh, Jonghyun, Hassan, Ahmed, Yeo, Injune, Kasichainula, Kishore, Seok, Mingoo, Seo, Jae-Sun, Cao, Yu
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	Piscataway IEEE 2024 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	3-D stacking Algorithms Artificial intelligence Co-design Computer architecture Data compression Data transmission dynamic vision sensor (DVS) in-memory computing (IMC) in-sensor computing Power consumption Power management Real time Semiconductor device measurement Sensor arrays Three-dimensional displays Through-silicon vias Time compression Voltage control Weight measurement
ISSN:	2573-9603, 2573-9603
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