3-D In-Sensor Computing for Real-Time DVS Data Compression: 65-nm Hardware-Algorithm Co-Design

Traditional IO links are insufficient to transport high volume of image sensor data, under stringent power and latency constraints. To address this, we demonstrate a low latency, low power in-sensor computing architecture to compress the data from a 3D-stacked dynamic vision sensor (DVS). In this de...

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Vydáno v:	IEEE solid-state circuits letters Ročník 7; s. 119 - 122
Hlavní autoři:	Nair, Gopikrishnan R., Nalla, Pragnya S., Krishnan, Gokul, Anupreetham, Oh, Jonghyun, Hassan, Ahmed, Yeo, Injune, Kasichainula, Kishore, Seok, Mingoo, Seo, Jae-Sun, Cao, Yu
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	Piscataway IEEE 2024 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:	3-D stacking Algorithms Artificial intelligence Co-design Computer architecture Data compression Data transmission dynamic vision sensor (DVS) in-memory computing (IMC) in-sensor computing Power consumption Power management Real time Semiconductor device measurement Sensor arrays Three-dimensional displays Through-silicon vias Time compression Voltage control Weight measurement
ISSN:	2573-9603, 2573-9603
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Abstract	Traditional IO links are insufficient to transport high volume of image sensor data, under stringent power and latency constraints. To address this, we demonstrate a low latency, low power in-sensor computing architecture to compress the data from a 3D-stacked dynamic vision sensor (DVS). In this design, we adopt a 4-bit autoencoder algorithm and implement it on an AI computing layer with in-memory computing (IMC) to enable real-time compression of DVS data. To support 3-D integration, this architecture is optimized to handle the unique constraints, including footprint to match the size of the sensor array, low latency to manage the continuous data stream, and low-power consumption to avoid thermal issues. Our prototype chip in 65-nm CMOS demonstrates the new concept of 3-D in-sensor computing, achieving < 6 mW power consumption at 1-10 MHz operating frequency, and<inline-formula> <tex-math notation="LaTeX">10\times </tex-math></inline-formula> compression ratio on <inline-formula> <tex-math notation="LaTeX">256\times 256 </tex-math></inline-formula> DVS pixels.
AbstractList	Traditional IO links are insufficient to transport high volume of image sensor data, under stringent power and latency constraints. To address this, we demonstrate a low latency, low power in-sensor computing architecture to compress the data from a 3D-stacked dynamic vision sensor (DVS). In this design, we adopt a 4-bit autoencoder algorithm and implement it on an AI computing layer with in-memory computing (IMC) to enable real-time compression of DVS data. To support 3-D integration, this architecture is optimized to handle the unique constraints, including footprint to match the size of the sensor array, low latency to manage the continuous data stream, and low-power consumption to avoid thermal issues. Our prototype chip in 65-nm CMOS demonstrates the new concept of 3-D in-sensor computing, achieving Traditional IO links are insufficient to transport high volume of image sensor data, under stringent power and latency constraints. To address this, we demonstrate a low latency, low power in-sensor computing architecture to compress the data from a 3D-stacked dynamic vision sensor (DVS). In this design, we adopt a 4-bit autoencoder algorithm and implement it on an AI computing layer with in-memory computing (IMC) to enable real-time compression of DVS data. To support 3-D integration, this architecture is optimized to handle the unique constraints, including footprint to match the size of the sensor array, low latency to manage the continuous data stream, and low-power consumption to avoid thermal issues. Our prototype chip in 65-nm CMOS demonstrates the new concept of 3-D in-sensor computing, achieving < 6 mW power consumption at 1-10 MHz operating frequency, and<inline-formula> <tex-math notation="LaTeX">10\times </tex-math></inline-formula> compression ratio on <inline-formula> <tex-math notation="LaTeX">256\times 256 </tex-math></inline-formula> DVS pixels.
Author	Seo, Jae-Sun Oh, Jonghyun Nair, Gopikrishnan R. Krishnan, Gokul Anupreetham Seok, Mingoo Nalla, Pragnya S. Cao, Yu Yeo, Injune Kasichainula, Kishore Hassan, Ahmed
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SubjectTerms	3-D stacking Algorithms Artificial intelligence Co-design Computer architecture Data compression Data transmission dynamic vision sensor (DVS) in-memory computing (IMC) in-sensor computing Power consumption Power management Real time Semiconductor device measurement Sensor arrays Three-dimensional displays Through-silicon vias Time compression Voltage control Weight measurement
Title	3-D In-Sensor Computing for Real-Time DVS Data Compression: 65-nm Hardware-Algorithm Co-Design
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