Nair, G. R., Nalla, P. S., Krishnan, G., Anupreetham, Oh, J., Hassan, A., . . . Cao, Y. (2024). 3-D In-Sensor Computing for Real-Time DVS Data Compression: 65-nm Hardware-Algorithm Co-Design. IEEE solid-state circuits letters, 7, 119-122. https://doi.org/10.1109/LSSC.2024.3375110
Chicago-Zitierstil (17. Ausg.)Nair, Gopikrishnan R., et al. "3-D In-Sensor Computing for Real-Time DVS Data Compression: 65-nm Hardware-Algorithm Co-Design." IEEE Solid-state Circuits Letters 7 (2024): 119-122. https://doi.org/10.1109/LSSC.2024.3375110.
MLA-Zitierstil (9. Ausg.)Nair, Gopikrishnan R., et al. "3-D In-Sensor Computing for Real-Time DVS Data Compression: 65-nm Hardware-Algorithm Co-Design." IEEE Solid-state Circuits Letters, vol. 7, 2024, pp. 119-122, https://doi.org/10.1109/LSSC.2024.3375110.