MALOC: A Fully Pipelined FPGA Accelerator for Convolutional Neural Networks With All Layers Mapped on Chip

Recently, field-programmable gate arrays (FPGAs) have been widely used in the implementations of hardware accelerator for convolutional neural networks (CNNs). However, most of these existing accelerators are designed in the same idea as their ASIC counterparts, in which all operations from differen...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems Jg. 37; H. 11; S. 2601 - 2612
Hauptverfasser:	Gong, Lei, Wang, Chao, Li, Xi, Chen, Huaping, Zhou, Xuehai
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.11.2018 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Accelerators Artificial neural networks Computational efficiency Computational modeling Computer architecture Computing time Convolutional neural network (CNN) Convolutional neural networks design space exploration (DSE) Efficiency Embedded systems Field programmable gate arrays field-programmable gate array (FPGA)-based accelerator Gate arrays Hardware Neural networks Optimization pipeline Pipelines programming framework Redundancy redundancy elimination Space exploration System-on-chip
ISSN:	0278-0070, 1937-4151
Online-Zugang:	Volltext
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