MALOC: A Fully Pipelined FPGA Accelerator for Convolutional Neural Networks With All Layers Mapped on Chip

Recently, field-programmable gate arrays (FPGAs) have been widely used in the implementations of hardware accelerator for convolutional neural networks (CNNs). However, most of these existing accelerators are designed in the same idea as their ASIC counterparts, in which all operations from differen...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems Jg. 37; H. 11; S. 2601 - 2612
Hauptverfasser:	Gong, Lei, Wang, Chao, Li, Xi, Chen, Huaping, Zhou, Xuehai
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.11.2018 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Accelerators Artificial neural networks Computational efficiency Computational modeling Computer architecture Computing time Convolutional neural network (CNN) Convolutional neural networks design space exploration (DSE) Efficiency Embedded systems Field programmable gate arrays field-programmable gate array (FPGA)-based accelerator Gate arrays Hardware Neural networks Optimization pipeline Pipelines programming framework Redundancy redundancy elimination Space exploration System-on-chip
ISSN:	0278-0070, 1937-4151
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Abstract	Recently, field-programmable gate arrays (FPGAs) have been widely used in the implementations of hardware accelerator for convolutional neural networks (CNNs). However, most of these existing accelerators are designed in the same idea as their ASIC counterparts, in which all operations from different layers are mapped to the same hardware units and working in a multiplexed way. This manner does not take full advantage of reconfigurability and customizability of FPGAs, resulting in a certain degree of computational efficiency degradation. In this paper, we propose a new architecture for FPGA-based CNN accelerator that maps all the layers to their own on-chip units and working concurrently as a pipeline. A comprehensive mapping and optimizing methodology based on establishing roofline model oriented optimization model is proposed, which can achieve maximum resource utilization as well as optimal computational efficiency. Besides, to ease the programming burden, we propose a design framework which can provide a one-stop function for developers to generate the accelerator with our optimizing methodology. We evaluate our proposal by implementing different modern CNN models on Xilinx Zynq-7020 and Virtex-7 690t FPGA platforms. Experimental results show that our implementations can achieve a peak performance of 910.2 GOPS on Virtex-7 690t, and 36.36 GOP/s/W energy efficiency on Zynq-7020, which are superior to the previous approaches.
AbstractList	Recently, field-programmable gate arrays (FPGAs) have been widely used in the implementations of hardware accelerator for convolutional neural networks (CNNs). However, most of these existing accelerators are designed in the same idea as their ASIC counterparts, in which all operations from different layers are mapped to the same hardware units and working in a multiplexed way. This manner does not take full advantage of reconfigurability and customizability of FPGAs, resulting in a certain degree of computational efficiency degradation. In this paper, we propose a new architecture for FPGA-based CNN accelerator that maps all the layers to their own on-chip units and working concurrently as a pipeline. A comprehensive mapping and optimizing methodology based on establishing roofline model oriented optimization model is proposed, which can achieve maximum resource utilization as well as optimal computational efficiency. Besides, to ease the programming burden, we propose a design framework which can provide a one-stop function for developers to generate the accelerator with our optimizing methodology. We evaluate our proposal by implementing different modern CNN models on Xilinx Zynq-7020 and Virtex-7 690t FPGA platforms. Experimental results show that our implementations can achieve a peak performance of 910.2 GOPS on Virtex-7 690t, and 36.36 GOP/s/W energy efficiency on Zynq-7020, which are superior to the previous approaches.
Author	Zhou, Xuehai Gong, Lei Wang, Chao Li, Xi Chen, Huaping
Author_xml	– sequence: 1 givenname: Lei orcidid: 0000-0002-8391-5526 surname: Gong fullname: Gong, Lei email: leigong0203@mail.ustc.edu.cn organization: School of Computer Science and Technology, University of Science and Technology of China, Hefei, China – sequence: 2 givenname: Chao orcidid: 0000-0002-9403-5575 surname: Wang fullname: Wang, Chao email: cswang@ustc.edu.cn organization: School of Computer Science and Technology, University of Science and Technology of China, Hefei, China – sequence: 3 givenname: Xi surname: Li fullname: Li, Xi email: llxx@ustc.edu.cn organization: School of Computer Science and Technology, University of Science and Technology of China, Hefei, China – sequence: 4 givenname: Huaping surname: Chen fullname: Chen, Huaping email: hpchen@ustc.edu.cn organization: School of Software Engineering, University of Science and Technology of China, Hefei, China – sequence: 5 givenname: Xuehai orcidid: 0000-0002-8360-3143 surname: Zhou fullname: Zhou, Xuehai email: xhzhou@ustc.edu.cn organization: School of Computer Science and Technology, University of Science and Technology of China, Hefei, China
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SubjectTerms	Accelerators Artificial neural networks Computational efficiency Computational modeling Computer architecture Computing time Convolutional neural network (CNN) Convolutional neural networks design space exploration (DSE) Efficiency Embedded systems Field programmable gate arrays field-programmable gate array (FPGA)-based accelerator Gate arrays Hardware Neural networks Optimization pipeline Pipelines programming framework Redundancy redundancy elimination Space exploration System-on-chip
Title	MALOC: A Fully Pipelined FPGA Accelerator for Convolutional Neural Networks With All Layers Mapped on Chip
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