Zhang, Z., Arcaini, P., & Xie, X. (2022). Online Reset for Signal Temporal Logic Monitoring. IEEE transactions on computer-aided design of integrated circuits and systems, 41(11), 4421-4432. https://doi.org/10.1109/TCAD.2022.3197693
Citácia podle Chicago (17th ed.)Zhang, Zhenya, Paolo Arcaini, a Xuan Xie. "Online Reset for Signal Temporal Logic Monitoring." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems 41, no. 11 (2022): 4421-4432. https://doi.org/10.1109/TCAD.2022.3197693.
Citácia podľa MLA (8th ed.)Zhang, Zhenya, et al. "Online Reset for Signal Temporal Logic Monitoring." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 41, no. 11, 2022, pp. 4421-4432, https://doi.org/10.1109/TCAD.2022.3197693.
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