Synthesizing Formal Network Specifications From Input-Output Examples

We propose, a tool that synthesizes network specifications in a declarative logic programming language from input-output examples. aims to accelerate the adoption of formal verification in networking practice, by reducing the effort and expertise required to specify network models or properties. aim...

Celý popis

Uložené v:

Podrobná bibliografia
Vydané v:	IEEE/ACM transactions on networking Ročník 31; číslo 3; s. 1 - 16
Hlavní autori:	Chen, Haoxian, Wu, Chenyuan, Zhao, Andrew, Raghothaman, Mukund, Naik, Mayur, Loo, Boon Thau
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York IEEE 01.06.2023 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Benchmark testing Consensus protocol Logic programming Network protocol program synthesis Programming languages Robustness (mathematics) Routing protocols Runtime Search algorithms Security Semantics Solution space Specifications Synthesis Task analysis Verification
ISSN:	1063-6692, 1558-2566
On-line prístup:	Získať plný text
Tagy:	Pridať tag Žiadne tagy, Buďte prvý, kto otaguje tento záznam!

Buďte prvý, kto okomentuje tento záznam!