Synthesizing Formal Network Specifications From Input-Output Examples

We propose, a tool that synthesizes network specifications in a declarative logic programming language from input-output examples. aims to accelerate the adoption of formal verification in networking practice, by reducing the effort and expertise required to specify network models or properties. aim...

Full description

Saved in:

Bibliographic Details
Published in:	IEEE/ACM transactions on networking Vol. 31; no. 3; pp. 1 - 16
Main Authors:	Chen, Haoxian, Wu, Chenyuan, Zhao, Andrew, Raghothaman, Mukund, Naik, Mayur, Loo, Boon Thau
Format:	Journal Article
Language:	English
Published:	New York IEEE 01.06.2023 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Benchmark testing Consensus protocol Logic programming Network protocol program synthesis Programming languages Robustness (mathematics) Routing protocols Runtime Search algorithms Security Semantics Solution space Specifications Synthesis Task analysis Verification
ISSN:	1063-6692, 1558-2566
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!

Be the first to leave a comment!