APA (7th ed.) Citation

Yu, C., Zhang, X., Liu, D., Ciesielski, M., & Holcomb, D. (2017). Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits. IEEE transactions on computer-aided design of integrated circuits and systems, 36(10), 1647-1659. https://doi.org/10.1109/TCAD.2017.2652220

Chicago Style (17th ed.) Citation

Yu, Cunxi, Xiangyu Zhang, Duo Liu, Maciej Ciesielski, and Daniel Holcomb. "Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems 36, no. 10 (2017): 1647-1659. https://doi.org/10.1109/TCAD.2017.2652220.

MLA (9th ed.) Citation

Yu, Cunxi, et al. "Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 36, no. 10, 2017, pp. 1647-1659, https://doi.org/10.1109/TCAD.2017.2652220.