Efficient Coding Architectures for Reed-Solomon and Low-Density Parity-Check Decoders for Magnetic and Other Data Storage Systems

High-performance error correction codes are used in high-density data storage devices to overcome noise and channel impairments. In this paper, we develop novel and efficient decoding architectures for Reed-Solomon (RS) and low-density parity-check (LDPC) codes that are used in almost all data stora...

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Veröffentlicht in:	IEEE transactions on magnetics Jg. 54; H. 2; S. 1 - 15
Hauptverfasser:	Mondal, Arijit, Thatimattala, Satyannarayana, Yalamaddi, Vamshi Krishna, Garani, Shayan Srinivasa
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.02.2018 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Berlekamp–Massey (BM) algorithm Codes Coding Computer architecture Data storage Decoders Decoding Delays Density Electronic devices Engine blocks Error correcting codes Error correction error correction codes (ECC) field programmable gate array (FPGA) Field programmable gate arrays high speed Kintex-7 FPGA layered min-sum low complexity low latency low-density parity-check (LDPC) Magnetism Measurement Noise levels non-uniform quantization (NUQ) Parallel processing Parity Parity check codes Polynomials Rams Reed–Solomon (RS) decoder State of the art Storage systems Throughput
ISSN:	0018-9464, 1941-0069
Online-Zugang:	Volltext
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