Data Compression for Image Sensor Arrays Using a 15-bit Two-Step Sigma-Delta ADC

This paper reports a readout integrated circuit with embedded data compression function for image sensors. Data compression is realized by adding a comparator in a two-step incremental sigma-delta analog-to-digital converter (ADC) with a fully floating double sampling integrator. The output differen...

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Vydané v:	IEEE sensors journal Ročník 14; číslo 9; s. 2989 - 2998
Hlavní autori:	Yue, Mengyun, Wu, Dong, Wang, Zheyao
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York IEEE 01.09.2014 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Clocks Data compression Image coding Image sensors Sensor arrays Sigma-delta modulation Image redundancy compressed sensing fully-floating integrator Sigma - Delta ADC
ISSN:	1530-437X, 1558-1748
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