Data Compression for Image Sensor Arrays Using a 15-bit Two-Step Sigma-Delta ADC
This paper reports a readout integrated circuit with embedded data compression function for image sensors. Data compression is realized by adding a comparator in a two-step incremental sigma-delta analog-to-digital converter (ADC) with a fully floating double sampling integrator. The output differen...
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| Veröffentlicht in: | IEEE sensors journal Jg. 14; H. 9; S. 2989 - 2998 |
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| Hauptverfasser: | , , |
| Format: | Journal Article |
| Sprache: | Englisch |
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New York
IEEE
01.09.2014
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
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| ISSN: | 1530-437X, 1558-1748 |
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| Abstract | This paper reports a readout integrated circuit with embedded data compression function for image sensors. Data compression is realized by adding a comparator in a two-step incremental sigma-delta analog-to-digital converter (ADC) with a fully floating double sampling integrator. The output difference between two adjacent pixels is compared with a predefined threshold using the comparator to detect redundant pixels. Once the difference is smaller than the threshold, indicating a redundant pixel, the AD conversion is omitted and the redundant information is stored using a Boolean variable. Thus, the conversion speed can be improved and the storage space is saved. An ADC test vehicle with an \(8 \times 8\) array has been fabricated using 0.5-\(\mu \) m CMOS technology. Measurement results show that the frame rate of the image sensor is 10%-236% faster than conventional ADC, and data compression ratios between 1 and 5 are achieved for images with different redundancy. The advantages of this on-chip image compression are the embedded and simple circuits, considerable speed and storage space improvement, and low power consumption. The preliminary results have demonstrated the feasibility and the effectiveness of the proposed compression method. |
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| AbstractList | This paper reports a readout integrated circuit with embedded data compression function for image sensors. Data compression is realized by adding a comparator in a two-step incremental sigma-delta analog-to-digital converter (ADC) with a fully floating double sampling integrator. The output difference between two adjacent pixels is compared with a predefined threshold using the comparator to detect redundant pixels. Once the difference is smaller than the threshold, indicating a redundant pixel, the AD conversion is omitted and the redundant information is stored using a Boolean variable. Thus, the conversion speed can be improved and the storage space is saved. An ADC test vehicle with an [Formula Omitted] array has been fabricated using 0.5-[Formula Omitted]m CMOS technology. Measurement results show that the frame rate of the image sensor is 10%-236% faster than conventional ADC, and data compression ratios between 1 and 5 are achieved for images with different redundancy. The advantages of this on-chip image compression are the embedded and simple circuits, considerable speed and storage space improvement, and low power consumption. The preliminary results have demonstrated the feasibility and the effectiveness of the proposed compression method. [PUBLICATION ABSTRACT] This paper reports a readout integrated circuit with embedded data compression function for image sensors. Data compression is realized by adding a comparator in a two-step incremental sigma-delta analog-to-digital converter (ADC) with a fully floating double sampling integrator. The output difference between two adjacent pixels is compared with a predefined threshold using the comparator to detect redundant pixels. Once the difference is smaller than the threshold, indicating a redundant pixel, the AD conversion is omitted and the redundant information is stored using a Boolean variable. Thus, the conversion speed can be improved and the storage space is saved. An ADC test vehicle with an \(8 \times 8\) array has been fabricated using 0.5-\(\mu \) m CMOS technology. Measurement results show that the frame rate of the image sensor is 10%-236% faster than conventional ADC, and data compression ratios between 1 and 5 are achieved for images with different redundancy. The advantages of this on-chip image compression are the embedded and simple circuits, considerable speed and storage space improvement, and low power consumption. The preliminary results have demonstrated the feasibility and the effectiveness of the proposed compression method. |
| Author | Mengyun Yue Dong Wu Zheyao Wang |
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| Cites_doi | 10.1109/TCOM.1978.1094144 10.1109/TIT.2007.909108 10.1109/4.280701 10.1109/JSEN.2011.2158818 10.1109/JSEN.2008.926923 10.1109/JSSC.2009.2016693 10.1109/5.542410 10.1109/JSEN.2010.2089447 10.1109/79.952804 10.1109/CICC.2006.320945 10.1109/JSEN.2008.2008407 10.1109/JSSC.2002.804334 10.1109/16.628829 10.1109/CICC.2007.4405857 10.1109/4.902758 10.1002/mrm.21391 10.1109/TMM.2010.2100374 10.1109/JSEN.2012.2199749 10.1109/TIT.2006.871582 10.1109/TIT.2005.862083 10.1109/TBME.2011.2156795 10.1109/JSEN.2009.2013917 10.1109/EMRTW.2005.195691 10.1109/JSSC.2011.2179451 10.1109/ISSCC.1994.344659 10.1109/TCSI.2005.844233 10.1109/ISCAS.2004.1328250 10.1109/TIT.2008.920190 10.1109/JSSC.2007.907191 10.1117/12.719171 10.1109/JSEN.2011.2177966 10.1016/0031-3203(84)90033-5 10.1109/83.136597 10.1155/2010/920693 10.1109/VECIMS.2005.1567564 10.1109/JSEN.2009.2029814 10.1109/TCSI.2010.2097652 10.1109/4.643649 10.1109/4.643661 |
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| SubjectTerms | Clocks Data compression Image coding Image sensors Sensor arrays Sigma-delta modulation |
| Title | Data Compression for Image Sensor Arrays Using a 15-bit Two-Step Sigma-Delta ADC |
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