Learning in Memristive Neural Network Architectures Using Analog Backpropagation Circuits

The on-chip implementation of learning algorithms would speed up the training of neural networks in crossbar arrays. The circuit level design and implementation of a back-propagation algorithm using gradient descent operation for neural network architectures is an open problem. In this paper, we pro...

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Vydáno v:IEEE transactions on circuits and systems. I, Regular papers Ročník 66; číslo 2; s. 719 - 732
Hlavní autoři: Krestinskaya, Olga, Salama, Khaled Nabil, James, Alex Pappachen
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York IEEE 01.02.2019
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
Analog circuits
Artificial neural networks
Back propagation
Back propagation networks
Backpropagation
Backpropagation algorithms
binary neural network
Biological neural networks
Circuit design
CMOS
Computer architecture
crossbar
deep neural network
Hardware
hierarchical temporal memory
learning
long-short term memory
Machine learning
memristor
Memristors
multiple neural network
Neural networks
Titanium dioxide
ISSN:1549-8328, 1558-0806
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Shrnutí:The on-chip implementation of learning algorithms would speed up the training of neural networks in crossbar arrays. The circuit level design and implementation of a back-propagation algorithm using gradient descent operation for neural network architectures is an open problem. In this paper, we propose analog backpropagation learning circuits for various memristive learning architectures, such as deep neural network, binary neural network, multiple neural network, hierarchical temporal memory, and long short-term memory. The circuit design and verification are done using TSMC 180-nm CMOS process models and TiO 2 -based memristor models. The application level validations of the system are done using XOR problem, MNIST character, and Yale face image databases.
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content type line 14
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2018.2866510