Processing Near Sensor Architecture in Mixed-Signal Domain With CMOS Image Sensor of Convolutional-Kernel-Readout Method

In the era of Artificial Intelligence (AI), bio-inspired perceptual computing system design brings favorable opportunities, while still facing considerable challenges in the meantime. Especially for tasks of image recognition in power-limited vision-based Internet of Things (IoT) devices, energy con...

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Veröffentlicht in:IEEE transactions on circuits and systems. I, Regular papers Jg. 67; H. 2; S. 389 - 400
Hauptverfasser: Chen, Zhe, Zhu, Huifeng, Ren, Erxiang, Liu, Zheyu, Jia, Kaige, Luo, Li, Zhang, Xuan, Wei, Qi, Qiao, Fei, Liu, Xinjun, Yang, Huazhong
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.02.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Algorithms
Analog to digital conversion
Analog to digital converters
Architecture
Artificial intelligence
binarized-weight neural network
Biomimetics
Circuits
CMOS
CMOS image sensors
Computer architecture
Convolution
Domains
Energy conversion efficiency
Energy efficiency
Energy management
Fault tolerance
Internet of Things
Kernel
Kernels
lower power IoT
Neural networks
Object recognition
Power consumption
Power efficiency
Power management
processing near sensor
Sensor arrays
Sensors
Signal processing
Smart CMOS image sensor
Systems design
Task analysis
Vision
Visual perception
Visual signals
ISSN:1549-8328, 1558-0806
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Zusammenfassung:In the era of Artificial Intelligence (AI), bio-inspired perceptual computing system design brings favorable opportunities, while still facing considerable challenges in the meantime. Especially for tasks of image recognition in power-limited vision-based Internet of Things (IoT) devices, energy constraints due to the end of Dennard scaling limit the performance of Neural Network (NN) algorithms on popular digital platforms, which would not reach the energy efficiency requirement for embedded AI applications. In this paper, a processing near sensor architecture in mixed-signal domain with CMOS Image Sensor (CIS) of convolutional-kernel-readout method is proposed. Visual data is collected from a smart CIS, which can realize maximum <inline-formula> <tex-math notation="LaTeX">5 \times 5 </tex-math></inline-formula> kernel-readout with minimum one slide step for convolutional operations. The outputs of CIS are directly processed by analog processing units locating near CIS without the constraint of digital clock and bottleneck of Analog-to-Digital Converter (ADC). By analyzing the effects of analog noise on classification accuracy, we further evaluate the fault-tolerance of the system to circuit noise and the device imperfection, such as mismatch and process variation. A mixed-signal visual perception chip is fabricated with a <inline-formula> <tex-math notation="LaTeX">32\times32 </tex-math></inline-formula> image sensor and a Binarized Neural Network (BNN) processing array integrated with SMIC 180nm standard CMOS mixed-signal process. Measurement results show up to 545.4 GOPS/W energy efficiency with 1.8mW power consumption taking the advantages of ADC-free processing architecture. This work provides a promising alternative for low-power vision-based IoT intelligent applications.
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ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2019.2937227