A (21150, 19050) GC-LDPC Decoder for NAND Flash Applications

In this paper, a (21150, 19050) globally-coupled low-density parity check (GC-LDPC) code designed for NAND flash memories is presented. The proposed LDPC code comprises three disjoint subcodes which can be decoded independently. This highly structural parity check matrix contributes to efficient dec...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Vol. 66; no. 3; pp. 1219 - 1230
Main Authors: Liao, Yen-Chin, Lin, Chien, Chang, Hsie-Chia, Lin, Shu
Format: Journal Article
Language:English
Published: New York IEEE 01.03.2019
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Collaboration
Critical path
Decoding
emerging memory ECC
Error correction codes
Flash memories
Flow control
Globally-coupled LDPC codes
Iterative algorithms
Iterative decoding
Low density parity check codes
Parity
two-phase local/global iterative decoding
ISSN:1549-8328, 1558-0806
Online Access:Get full text
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Summary:In this paper, a (21150, 19050) globally-coupled low-density parity check (GC-LDPC) code designed for NAND flash memories is presented. The proposed LDPC code comprises three disjoint subcodes which can be decoded independently. This highly structural parity check matrix contributes to efficient decoder implementation and flexible decoding flow control. Moreover, a two-phase local/global decoding procedure optimized for the proposed GC-LDPC code is introduced. Scenarios of collaborative decoding that leverages the special code structures are discussed. In the proposed decoder architecture, the pipelined processing elements with scheduling are employed to reduce the critical path and decoding latency as well. Implemented in UMC 65 nm process, the post-layout simulation shows a maximum decoding throughput of 4.32 Gb/s with the chip area 3.376 mm 2 .
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ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2018.2875311