A Novel Data-Partitioning Algorithm for Performance Optimization of Data-Parallel Applications on Heterogeneous HPC Platforms

Modern HPC platforms have become highly heterogeneous owing to tight integration of multicore CPUs and accelerators (such as Graphics Processing Units, Intel Xeon Phis, or Field-Programmable Gate Arrays) empowering them to maximize the dominant objectives of performance and energy efficiency. Due to...

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Bibliographic Details
Published in:	IEEE transactions on parallel and distributed systems Vol. 29; no. 10; pp. 2176 - 2190
Main Authors:	Khaleghzadeh, Hamidreza, Manumachu, Ravindranath Reddy, Lastovetsky, Alexey
Format:	Journal Article
Language:	English
Published:	New York IEEE 01.10.2018 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Accelerators Algorithms Bus interconnections Central Processing Unit Central processing units Computational modeling CPUs data partitioning data-parallel applications Fast Fourier transformations Field programmable gate arrays Fourier transforms Gate arrays GPU Graphics processing units Heterogeneous HPC platforms Intel Xeon Phi Kernel load balancing Load modeling Mathematical models Microprocessors multicore CPU Multicore processing Optimization Partitioning performance optimization Platforms
ISSN:	1045-9219, 1558-2183
Online Access:	Get full text
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