Exploring GPU-Accelerated Routing for FPGAs

Field Programmable Gate Arrays (FPGAs) are reconfigurable architectures able to provide a good balance between energy efficiency and flexibility with respect to CPUs and ASICs. The main drawback in using FPGAs, however, is their timing-consuming routing process, significantly hindering the designer...

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Vydané v:	IEEE transactions on parallel and distributed systems Ročník 30; číslo 6; s. 1331 - 1345
Hlavní autori:	Shen, Minghua, Luo, Guojie, Xiao, Nong
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York IEEE 01.06.2019 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Acceleration Algorithms Dynamic programming Energy conversion efficiency Field programmable gate arrays FPGAs Gate arrays GPU parallelization Graph theory Graphics processing units Hardware Heuristic algorithms Nickel Parallel processing reconfigurable architectures Routing Shortest-path problems Size reduction
ISSN:	1045-9219, 1558-2183
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Abstract	Field Programmable Gate Arrays (FPGAs) are reconfigurable architectures able to provide a good balance between energy efficiency and flexibility with respect to CPUs and ASICs. The main drawback in using FPGAs, however, is their timing-consuming routing process, significantly hindering the designer productivity. An emerging solution to this problem is to accelerate the routing by parallelization. Existing attempts of parallelizing the FPGA routing either do not fully exploit the parallelism or suffer from an excessive quality loss. Massive parallelism using GPUs has the potential to solve this issue but faces non-trivial challenges. To cope with these challenges, this paper explores GPU-accelerated routing approach for FPGAs. We leverage the idea of problem size reduction by limiting the single-net routing in a small subgraph rather than in an entire graph, further enabling the GPU-friendly shortest path algorithm to be used in FPGA routing. We maintain the convergence after problem size reduction by using the dynamic expansion of the routing resource subgraph, where the routing region of subgraph will be progressively expanded to find a feasible solution to each net. In addition, we are based on a GPU platform to explore the fine-grained single-net parallel routing in three ways and propose a hybrid approach to combine the static and dynamic parallelization for better speedup in FPGA routing. To explore the coarse-grained multi-net parallelization, We propose a dynamic programming-based partitioning algorithm to parallelize the routing of multiple nets while generating the equivalent routing results as the original single-net routing. Experimental results show that our proposed approach can provide an average of about 21.53× speedup on a single GPU with a tolerable loss in the routing quality and maintain a scalable speedup on large-scale routing resource graphs. To our knowledge, this is the first work to demonstrate the effectiveness of GPU-accelerated routing for FPGAs.
AbstractList	Field Programmable Gate Arrays (FPGAs) are reconfigurable architectures able to provide a good balance between energy efficiency and flexibility with respect to CPUs and ASICs. The main drawback in using FPGAs, however, is their timing-consuming routing process, significantly hindering the designer productivity. An emerging solution to this problem is to accelerate the routing by parallelization. Existing attempts of parallelizing the FPGA routing either do not fully exploit the parallelism or suffer from an excessive quality loss. Massive parallelism using GPUs has the potential to solve this issue but faces non-trivial challenges. To cope with these challenges, this paper explores GPU-accelerated routing approach for FPGAs. We leverage the idea of problem size reduction by limiting the single-net routing in a small subgraph rather than in an entire graph, further enabling the GPU-friendly shortest path algorithm to be used in FPGA routing. We maintain the convergence after problem size reduction by using the dynamic expansion of the routing resource subgraph, where the routing region of subgraph will be progressively expanded to find a feasible solution to each net. In addition, we are based on a GPU platform to explore the fine-grained single-net parallel routing in three ways and propose a hybrid approach to combine the static and dynamic parallelization for better speedup in FPGA routing. To explore the coarse-grained multi-net parallelization, We propose a dynamic programming-based partitioning algorithm to parallelize the routing of multiple nets while generating the equivalent routing results as the original single-net routing. Experimental results show that our proposed approach can provide an average of about 21.53× speedup on a single GPU with a tolerable loss in the routing quality and maintain a scalable speedup on large-scale routing resource graphs. To our knowledge, this is the first work to demonstrate the effectiveness of GPU-accelerated routing for FPGAs.
Author	Luo, Guojie Shen, Minghua Xiao, Nong
Author_xml	– sequence: 1 givenname: Minghua orcidid: 0000-0003-4747-8020 surname: Shen fullname: Shen, Minghua email: shenmh6@mail.sysu.edu.cn organization: School of Data and Computer Science, Sun Yat-Sen University, Guangzhou, China – sequence: 2 givenname: Guojie orcidid: 0000-0003-4932-3655 surname: Luo fullname: Luo, Guojie email: gluo@pku.edu.cn organization: Center for Energy-Efficient Computing and Applications, School of Electronics Engineering and Computer Science, Peking University, Beijing, China – sequence: 3 givenname: Nong surname: Xiao fullname: Xiao, Nong email: xiaon6@mail.sysu.edu.cn organization: School of Data and Computer Science, Sun Yat-Sen University, Guangzhou, China
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References	ref35 ref13 ref34 gupta (ref3) 2015 sedgewick (ref39) 2011 ref37 ref15 rose (ref43) 2014; 7 ref36 ref14 ref31 ref30 ref33 ref11 ref32 ref17 ref38 ref19 ref18 esmaeilzadeh (ref1) 2011 dehon (ref28) 2006 zhu (ref12) 2013 brewer (ref4) 2015 deng (ref23) 2013; 7 ref26 hoo (ref16) 2015 ref25 ref20 ref42 ref41 catanzaro (ref10) 2008 mcmurchie (ref9) 1995 ref21 bleiweiss (ref24) 2008 ref27 ref29 ref8 ref7 atasu (ref2) 2015 ref5 meyer (ref22) 1998 ref40 ovtcharov (ref6) 2015
References_xml	– ident: ref27 doi: 10.1109/IPDPS.2014.45 – start-page: 393 year: 1998 ident: ref22 article-title: Delta-stepping: A parallel single source shortest path algorithm publication-title: Proc European Symp Algorithms – ident: ref35 doi: 10.1145/1950413.1950447 – start-page: 143 year: 2006 ident: ref28 article-title: GraphStep: A system architecture for sparse-graph algorithm publication-title: Proc IEEE Symp Field Programm Custom Comput Mach – start-page: 1 year: 2013 ident: ref12 article-title: A novel net-partition-based multithreaded FPGA routing method publication-title: Proc IEEE Int Conf Field Programmable Logic Appl – ident: ref26 doi: 10.1109/TPDS.2015.2485994 – volume: 7 year: 2014 ident: ref43 article-title: VTR 7.0: Next generation architecture and CAD system for FPGAs publication-title: ACM Trans Reconfigurable Technol Syst – ident: ref34 doi: 10.1109/43.856973 – ident: ref20 doi: 10.1109/SAAHPC.2011.16 – ident: ref17 doi: 10.1145/1687399.1687451 – start-page: 111 year: 1995 ident: ref9 article-title: pathfinder: a negotiation-based performance-driven router for fpgas publication-title: Third International ACM Symposium on Field-Programmable Gate Arrays doi: 10.1109/FPGA.1995.242049 – ident: ref33 doi: 10.1145/2145816.2145832 – start-page: 365 year: 2011 ident: ref1 article-title: Dark silicon and the end of multicore scaling publication-title: 2011 38th Annual International Symposium on Computer Architecture (ISCA) ISCA – ident: ref18 doi: 10.1145/2847263.2847266 – year: 2015 ident: ref6 article-title: Accelerating deep convolutional neural networks using specialized hardware publication-title: White Paper – start-page: 12 year: 2008 ident: ref10 article-title: Parallelizaing CAD: A timely research agenda for EDA publication-title: Proc Annu ACM Des Autom Conf – start-page: 1 year: 2015 ident: ref16 article-title: ParaLaR: A parallel FPGA router based on lagrangian relaxation publication-title: Proc IEEE Int Conf Field Programmable Logic Appl – ident: ref21 doi: 10.1007/978-3-540-77220-0_21 – ident: ref8 doi: 10.1109/TEC.1961.5219222 – year: 2015 ident: ref3 article-title: Xeon+FPGA platform for the data center publication-title: Proc 4th Workshop Intersections Comput Archit Reconfigurable Logic (CARL) – ident: ref29 doi: 10.1145/3020078.3021732 – ident: ref38 doi: 10.1007/BFb0097950 – start-page: 65 year: 2008 ident: ref24 article-title: GPU accelerated pathfinding publication-title: Proc Symp Graph Hardware – ident: ref7 doi: 10.1145/2629579 – year: 2011 ident: ref39 publication-title: Algorithms – ident: ref11 doi: 10.1109/FPGA.1997.624617 – ident: ref5 doi: 10.1109/ISCA.2014.6853195 – volume: 7 start-page: 1 year: 2013 ident: ref23 article-title: Electronic design automation with graphic processors: A survey publication-title: Proc Int Conf Found Trends Electron Des Autom doi: 10.1561/1000000028 – ident: ref13 doi: 10.1109/FPT.2010.5681758 – ident: ref37 doi: 10.1109/IPDPSW.2015.130 – ident: ref40 doi: 10.1109/FCCM.2011.17 – ident: ref19 doi: 10.1109/FPL.2010.33 – year: 2015 ident: ref2 article-title: Accelerating text analytics queries on reconfigurable platforms publication-title: Proc 4th Workshop Intersections Comput Archit Reconfigurable Logic (CARL) – ident: ref32 doi: 10.1145/1993498.1993501 – ident: ref42 doi: 10.1145/1878961.1878966 – ident: ref25 doi: 10.1109/ICCD.2013.6657028 – ident: ref36 doi: 10.1109/FPGA.2002.1106675 – ident: ref41 doi: 10.1145/2380445.2380491 – year: 2015 ident: ref4 article-title: Convey's acceleration of the Memcached and Imagemagick applications publication-title: Proc 4th Workshop Intersections Comput Archit Reconfigurable Logic (CARL) – ident: ref15 doi: 10.1109/ICCAD.2015.7372558 – ident: ref31 doi: 10.1109/IISWC.2012.6402918 – ident: ref30 doi: 10.1007/978-1-4615-5145-4 – ident: ref14 doi: 10.1145/2593069.2593177
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SubjectTerms	Acceleration Algorithms Dynamic programming Energy conversion efficiency Field programmable gate arrays FPGAs Gate arrays GPU parallelization Graph theory Graphics processing units Hardware Heuristic algorithms Nickel Parallel processing reconfigurable architectures Routing Shortest-path problems Size reduction
Title	Exploring GPU-Accelerated Routing for FPGAs
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