Generative Multi-Symbol Architecture of the Binary Arithmetic Coder for UHDTV Video Encoders

Binary arithmetic coding is a key part of recent video compression standards. Its throughput is limited by the inherent dependencies existing in the algorithm. As a consequence, a higher bin parallelism leads to lower clock frequencies. This paper presents an architecture able to exceed limits exist...

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Vydané v:	IEEE transactions on circuits and systems. I, Regular papers Ročník 67; číslo 3; s. 891 - 902
Hlavný autor:	Pastuszak, Grzegorz
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York IEEE 01.03.2020 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Algorithms Arithmetic coding binary arithmetic coding Binary codes Bins CABAC Clocks Coders Computer architecture Encoding entropy coding FPGA H264/AVC H265/HEVC Registers Streaming media Symbols Throughput UHDTV Video compression video encoder VLSI
ISSN:	1549-8328, 1558-0806
On-line prístup:	Získať plný text
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