CIM-Spin: A Scalable CMOS Annealing Processor With Digital In-Memory Spin Operators and Register Spins for Combinatorial Optimization Problems

Recently, annealing processors based on the Ising model have received rising attention as efficient alternative hardware for solving combinatorial optimization problems. After mapping a problem to the hardware Ising model, we can observe the natural convergence behavior of the Ising model and find p...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits Vol. 57; no. 7; pp. 2263 - 2273
Main Authors: Su, Yuqi, Kim, Hyunjoon, Kim, Bongjin
Format: Journal Article
Language:English
Published: New York IEEE 01.07.2022
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Annealing
Annealing processor
Combinatorial analysis
combinatorial optimization problem (COP)
Computational modeling
Hardware
in-memory computing
Integrated circuit modeling
Ising model
max-cut problem
Microprocessors
Optimization
Random access memory
Semiconductor device modeling
ISSN:0018-9200, 1558-173X
Online Access:Get full text
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Summary:Recently, annealing processors based on the Ising model have received rising attention as efficient alternative hardware for solving combinatorial optimization problems. After mapping a problem to the hardware Ising model, we can observe the natural convergence behavior of the Ising model and find potential solutions to the problem. The quantum annealing processor has shown effectiveness in finding better solutions to the problems by using quantum bits (qubits) with annealing based on their quantum tunneling behaviors. However, the annealing processor based on the emerging quantum technology faces challenges such as limited scalability, high energy consumption, and operating costs due to the extremely low operating temperature. As a low-cost alternative, a CMOS annealing processor has been recently developed and drawn increasing attention thanks to the advantages over its quantum counterpart, including better scalability and lower energy consumption. In this work, we present a digital CMOS annealing processor with in-memory spin operators and register spins. The proposed CMOS annealing processor achieves ><inline-formula> <tex-math notation="LaTeX">10\times </tex-math></inline-formula> energy efficiency and faster operation than state-of-the-art works.
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ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2021.3139901