i-SRAM: Interleaved Wordlines for Vector Boolean Operations Using SRAMs

The generic approach toward SRAM based in-memory computations has been to activate multiple memory rows simultaneously and read out a logic function of the constituent rows. In general, these schemes introduce errors in computations due to their analog nature, limiting their usage to error-resilient...

Celý popis

Uložené v:

Podrobná bibliografia
Vydané v:	IEEE transactions on circuits and systems. I, Regular papers Ročník 67; číslo 12; s. 4651 - 4659
Hlavní autori:	Jaiswal, Akhilesh, Agrawal, Amogh, Ali, Mustafa F., Sharmin, Saima, Roy, Kaushik
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York IEEE 01.12.2020 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Arrays binary neural network Boolean Boolean algebra Encryption In-memory computing interleaved word-lines Layout Logic gates Machine learning Neural networks Proposals Random access memory SRAMs Stability Static random access memory Throughput von Neumann bottleneck
ISSN:	1549-8328, 1558-0806
On-line prístup:	Získať plný text
Tagy:	Pridať tag Žiadne tagy, Buďte prvý, kto otaguje tento záznam!

Buďte prvý, kto okomentuje tento záznam!