i-SRAM: Interleaved Wordlines for Vector Boolean Operations Using SRAMs

The generic approach toward SRAM based in-memory computations has been to activate multiple memory rows simultaneously and read out a logic function of the constituent rows. In general, these schemes introduce errors in computations due to their analog nature, limiting their usage to error-resilient...

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Veröffentlicht in:	IEEE transactions on circuits and systems. I, Regular papers Jg. 67; H. 12; S. 4651 - 4659
Hauptverfasser:	Jaiswal, Akhilesh, Agrawal, Amogh, Ali, Mustafa F., Sharmin, Saima, Roy, Kaushik
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.12.2020 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Arrays binary neural network Boolean Boolean algebra Encryption In-memory computing interleaved word-lines Layout Logic gates Machine learning Neural networks Proposals Random access memory SRAMs Stability Static random access memory Throughput von Neumann bottleneck
ISSN:	1549-8328, 1558-0806
Online-Zugang:	Volltext
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