i-SRAM: Interleaved Wordlines for Vector Boolean Operations Using SRAMs

The generic approach toward SRAM based in-memory computations has been to activate multiple memory rows simultaneously and read out a logic function of the constituent rows. In general, these schemes introduce errors in computations due to their analog nature, limiting their usage to error-resilient...

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Vydáno v:	IEEE transactions on circuits and systems. I, Regular papers Ročník 67; číslo 12; s. 4651 - 4659
Hlavní autoři:	Jaiswal, Akhilesh, Agrawal, Amogh, Ali, Mustafa F., Sharmin, Saima, Roy, Kaushik
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	New York IEEE 01.12.2020 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:	Arrays binary neural network Boolean Boolean algebra Encryption In-memory computing interleaved word-lines Layout Logic gates Machine learning Neural networks Proposals Random access memory SRAMs Stability Static random access memory Throughput von Neumann bottleneck
ISSN:	1549-8328, 1558-0806
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Abstract	The generic approach toward SRAM based in-memory computations has been to activate multiple memory rows simultaneously and read out a logic function of the constituent rows. In general, these schemes introduce errors in computations due to their analog nature, limiting their usage to error-resilient applications such as machine learning. In contrast, in-memory bulk bit-wise Boolean computations are suitable not only for error-resilient applications, but also those that require accurate computations like encryption. Prior works have indeed accomplished such bit-wise computations, however, they require modifications to the normal SRAM read operations leading to degraded read-stability or lower sense-margin. In this paper, we propose interleaving the word-lines (i-SRAM) as the basic approach for embedding bit-wise computations in SRAM arrays. Further, our i-SRAM read operation is identical to the normal memory read operation without loss of read-robustness or sense-margin. Even at deeply scaled nodes, as long as normal SRAM read stability is ascertained, the presented proposal works equally well. As opposed to prior works, this is a key benefactor in allowing the proposal to be seamlessly integrated in state-of-the-art SRAM compilers. We propose different configurations of i-SRAM for 6T and 8T-bit-cells, with minimal area overhead. We further demonstrate upto <inline-formula> <tex-math notation="LaTeX">\sim 2 \times </tex-math></inline-formula> improvement in energy and <inline-formula> <tex-math notation="LaTeX">\sim 8 \times </tex-math></inline-formula> improvement in throughput for a binary neural network (BNN) and <inline-formula> <tex-math notation="LaTeX">\sim 3.5 \times </tex-math></inline-formula> improvement in energy and <inline-formula> <tex-math notation="LaTeX">\sim 3 \times </tex-math></inline-formula> improvement in throughput for AES encryption using the proposed i-SRAM in a modified von-Neuamnn machine.
AbstractList	The generic approach toward SRAM based in-memory computations has been to activate multiple memory rows simultaneously and read out a logic function of the constituent rows. In general, these schemes introduce errors in computations due to their analog nature, limiting their usage to error-resilient applications such as machine learning. In contrast, in-memory bulk bit-wise Boolean computations are suitable not only for error-resilient applications, but also those that require accurate computations like encryption. Prior works have indeed accomplished such bit-wise computations, however, they require modifications to the normal SRAM read operations leading to degraded read-stability or lower sense-margin. In this paper, we propose interleaving the word-lines (i-SRAM) as the basic approach for embedding bit-wise computations in SRAM arrays. Further, our i-SRAM read operation is identical to the normal memory read operation without loss of read-robustness or sense-margin. Even at deeply scaled nodes, as long as normal SRAM read stability is ascertained, the presented proposal works equally well. As opposed to prior works, this is a key benefactor in allowing the proposal to be seamlessly integrated in state-of-the-art SRAM compilers. We propose different configurations of i-SRAM for 6T and 8T-bit-cells, with minimal area overhead. We further demonstrate upto [Formula Omitted] improvement in energy and [Formula Omitted] improvement in throughput for a binary neural network (BNN) and [Formula Omitted] improvement in energy and [Formula Omitted] improvement in throughput for AES encryption using the proposed i-SRAM in a modified von-Neuamnn machine. The generic approach toward SRAM based in-memory computations has been to activate multiple memory rows simultaneously and read out a logic function of the constituent rows. In general, these schemes introduce errors in computations due to their analog nature, limiting their usage to error-resilient applications such as machine learning. In contrast, in-memory bulk bit-wise Boolean computations are suitable not only for error-resilient applications, but also those that require accurate computations like encryption. Prior works have indeed accomplished such bit-wise computations, however, they require modifications to the normal SRAM read operations leading to degraded read-stability or lower sense-margin. In this paper, we propose interleaving the word-lines (i-SRAM) as the basic approach for embedding bit-wise computations in SRAM arrays. Further, our i-SRAM read operation is identical to the normal memory read operation without loss of read-robustness or sense-margin. Even at deeply scaled nodes, as long as normal SRAM read stability is ascertained, the presented proposal works equally well. As opposed to prior works, this is a key benefactor in allowing the proposal to be seamlessly integrated in state-of-the-art SRAM compilers. We propose different configurations of i-SRAM for 6T and 8T-bit-cells, with minimal area overhead. We further demonstrate upto <inline-formula> <tex-math notation="LaTeX">\sim 2 \times </tex-math></inline-formula> improvement in energy and <inline-formula> <tex-math notation="LaTeX">\sim 8 \times </tex-math></inline-formula> improvement in throughput for a binary neural network (BNN) and <inline-formula> <tex-math notation="LaTeX">\sim 3.5 \times </tex-math></inline-formula> improvement in energy and <inline-formula> <tex-math notation="LaTeX">\sim 3 \times </tex-math></inline-formula> improvement in throughput for AES encryption using the proposed i-SRAM in a modified von-Neuamnn machine.
Author	Sharmin, Saima Roy, Kaushik Agrawal, Amogh Ali, Mustafa F. Jaiswal, Akhilesh
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SubjectTerms	Arrays binary neural network Boolean Boolean algebra Encryption In-memory computing interleaved word-lines Layout Logic gates Machine learning Neural networks Proposals Random access memory SRAMs Stability Static random access memory Throughput von Neumann bottleneck
Title	i-SRAM: Interleaved Wordlines for Vector Boolean Operations Using SRAMs
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