i-SRAM: Interleaved Wordlines for Vector Boolean Operations Using SRAMs
The generic approach toward SRAM based in-memory computations has been to activate multiple memory rows simultaneously and read out a logic function of the constituent rows. In general, these schemes introduce errors in computations due to their analog nature, limiting their usage to error-resilient...
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| Published in: | IEEE transactions on circuits and systems. I, Regular papers Vol. 67; no. 12; pp. 4651 - 4659 |
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| Main Authors: | , , , , |
| Format: | Journal Article |
| Language: | English |
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IEEE
01.12.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
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| ISSN: | 1549-8328, 1558-0806 |
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| Abstract | The generic approach toward SRAM based in-memory computations has been to activate multiple memory rows simultaneously and read out a logic function of the constituent rows. In general, these schemes introduce errors in computations due to their analog nature, limiting their usage to error-resilient applications such as machine learning. In contrast, in-memory bulk bit-wise Boolean computations are suitable not only for error-resilient applications, but also those that require accurate computations like encryption. Prior works have indeed accomplished such bit-wise computations, however, they require modifications to the normal SRAM read operations leading to degraded read-stability or lower sense-margin. In this paper, we propose interleaving the word-lines (i-SRAM) as the basic approach for embedding bit-wise computations in SRAM arrays. Further, our i-SRAM read operation is identical to the normal memory read operation without loss of read-robustness or sense-margin. Even at deeply scaled nodes, as long as normal SRAM read stability is ascertained, the presented proposal works equally well. As opposed to prior works, this is a key benefactor in allowing the proposal to be seamlessly integrated in state-of-the-art SRAM compilers. We propose different configurations of i-SRAM for 6T and 8T-bit-cells, with minimal area overhead. We further demonstrate upto <inline-formula> <tex-math notation="LaTeX">\sim 2 \times </tex-math></inline-formula> improvement in energy and <inline-formula> <tex-math notation="LaTeX">\sim 8 \times </tex-math></inline-formula> improvement in throughput for a binary neural network (BNN) and <inline-formula> <tex-math notation="LaTeX">\sim 3.5 \times </tex-math></inline-formula> improvement in energy and <inline-formula> <tex-math notation="LaTeX">\sim 3 \times </tex-math></inline-formula> improvement in throughput for AES encryption using the proposed i-SRAM in a modified von-Neuamnn machine. |
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| AbstractList | The generic approach toward SRAM based in-memory computations has been to activate multiple memory rows simultaneously and read out a logic function of the constituent rows. In general, these schemes introduce errors in computations due to their analog nature, limiting their usage to error-resilient applications such as machine learning. In contrast, in-memory bulk bit-wise Boolean computations are suitable not only for error-resilient applications, but also those that require accurate computations like encryption. Prior works have indeed accomplished such bit-wise computations, however, they require modifications to the normal SRAM read operations leading to degraded read-stability or lower sense-margin. In this paper, we propose interleaving the word-lines (i-SRAM) as the basic approach for embedding bit-wise computations in SRAM arrays. Further, our i-SRAM read operation is identical to the normal memory read operation without loss of read-robustness or sense-margin. Even at deeply scaled nodes, as long as normal SRAM read stability is ascertained, the presented proposal works equally well. As opposed to prior works, this is a key benefactor in allowing the proposal to be seamlessly integrated in state-of-the-art SRAM compilers. We propose different configurations of i-SRAM for 6T and 8T-bit-cells, with minimal area overhead. We further demonstrate upto [Formula Omitted] improvement in energy and [Formula Omitted] improvement in throughput for a binary neural network (BNN) and [Formula Omitted] improvement in energy and [Formula Omitted] improvement in throughput for AES encryption using the proposed i-SRAM in a modified von-Neuamnn machine. The generic approach toward SRAM based in-memory computations has been to activate multiple memory rows simultaneously and read out a logic function of the constituent rows. In general, these schemes introduce errors in computations due to their analog nature, limiting their usage to error-resilient applications such as machine learning. In contrast, in-memory bulk bit-wise Boolean computations are suitable not only for error-resilient applications, but also those that require accurate computations like encryption. Prior works have indeed accomplished such bit-wise computations, however, they require modifications to the normal SRAM read operations leading to degraded read-stability or lower sense-margin. In this paper, we propose interleaving the word-lines (i-SRAM) as the basic approach for embedding bit-wise computations in SRAM arrays. Further, our i-SRAM read operation is identical to the normal memory read operation without loss of read-robustness or sense-margin. Even at deeply scaled nodes, as long as normal SRAM read stability is ascertained, the presented proposal works equally well. As opposed to prior works, this is a key benefactor in allowing the proposal to be seamlessly integrated in state-of-the-art SRAM compilers. We propose different configurations of i-SRAM for 6T and 8T-bit-cells, with minimal area overhead. We further demonstrate upto <inline-formula> <tex-math notation="LaTeX">\sim 2 \times </tex-math></inline-formula> improvement in energy and <inline-formula> <tex-math notation="LaTeX">\sim 8 \times </tex-math></inline-formula> improvement in throughput for a binary neural network (BNN) and <inline-formula> <tex-math notation="LaTeX">\sim 3.5 \times </tex-math></inline-formula> improvement in energy and <inline-formula> <tex-math notation="LaTeX">\sim 3 \times </tex-math></inline-formula> improvement in throughput for AES encryption using the proposed i-SRAM in a modified von-Neuamnn machine. |
| Author | Sharmin, Saima Roy, Kaushik Agrawal, Amogh Ali, Mustafa F. Jaiswal, Akhilesh |
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| Cites_doi | 10.1109/2.375174 10.1109/ISSCC.2018.8310397 10.1109/JSSC.2016.2642198 10.1109/ICASSP.2014.6855225 10.1109/TCSI.2020.2981901 10.1109/CICC.1992.591879 10.1109/TCSI.2019.2945617 10.1007/978-3-319-46493-0_32 10.1109/ISCA.2018.00040 10.1109/VLSIT.2018.8510687 10.1109/HPCA.2017.21 10.1109/JSSC.2017.2782087 10.1109/ISSCC.2019.8662435 10.1109/TCSI.2018.2848999 10.1109/JSSC.2018.2822703 10.1145/3007787.3001139 10.1145/3297858.3304049 10.1109/.2005.1469239 10.1109/JSSC.2018.2867275 10.1109/ISSCC.2019.8662392 |
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| References | ref13 ref15 ref14 ref10 (ref21) 2020 jaiswal (ref11) 2018 ref2 courbariaux (ref24) 2016 agrawal (ref12) 2018 ref17 ref16 ref19 ref18 dworkin (ref29) 2001 krizhevsky (ref25) 2009 (ref26) 2019 ref23 dong (ref1) 2017 ref20 ref28 ref27 ref8 ref7 ref9 ref4 ref3 ref6 ref5 (ref22) 2017 |
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| SubjectTerms | Arrays binary neural network Boolean Boolean algebra Encryption In-memory computing interleaved word-lines Layout Logic gates Machine learning Neural networks Proposals Random access memory SRAMs Stability Static random access memory Throughput von Neumann bottleneck |
| Title | i-SRAM: Interleaved Wordlines for Vector Boolean Operations Using SRAMs |
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