A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits
We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using carbon nanotube field-effect transistors (CNTFETs). The circuit structure uses the body effect to mitigate the ex...
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| Published in: | IEEE transactions on circuits and systems. I, Regular papers Vol. 67; no. 9; pp. 3138 - 3151 |
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| Main Authors: | , , , , |
| Format: | Journal Article |
| Language: | English |
| Published: |
New York
IEEE
01.09.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
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| ISSN: | 1549-8328, 1558-0806 |
| Online Access: | Get full text |
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| Abstract | We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using carbon nanotube field-effect transistors (CNTFETs). The circuit structure uses the body effect to mitigate the excessive power consumption for the third logic value. Energy-efficient ternary logic circuits are designed with a combination of synthesized low-power ternary logic gates. The proposed methodology is applicable to both unbalanced (0, 1, 2) and balanced (−1, 0, 1) ternary logic. To verify the improvement in energy efficiency, we have designed various ternary arithmetic logic circuits using the proposed methodology. The proposed ternary full adder has a significant improvement in the power-delay product (PDP) over previous designs. Ternary benchmark circuits have been designed to show that complex ternary functions can be designed to more efficient circuits with the proposed methodology. |
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| AbstractList | We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using carbon nanotube field-effect transistors (CNTFETs). The circuit structure uses the body effect to mitigate the excessive power consumption for the third logic value. Energy-efficient ternary logic circuits are designed with a combination of synthesized low-power ternary logic gates. The proposed methodology is applicable to both unbalanced (0, 1, 2) and balanced (−1, 0, 1) ternary logic. To verify the improvement in energy efficiency, we have designed various ternary arithmetic logic circuits using the proposed methodology. The proposed ternary full adder has a significant improvement in the power-delay product (PDP) over previous designs. Ternary benchmark circuits have been designed to show that complex ternary functions can be designed to more efficient circuits with the proposed methodology. |
| Author | Kim, Sunmean Kang, Seokhyeong Lee, Sung-Yun Park, Sunghye Kim, Kyung Rok |
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| SubjectTerms | body effect Carbon nanotubes Circuit design Circuits CNTFETs Complexity theory Energy efficiency Field effect transistors Gates (circuits) Integrated circuit interconnections Logic circuits Logic gates Logic synthesis logic synthesis methodology Methodology Multi-valued logic Multivalued logic Power consumption Semiconductor devices ternary logic circuits |
| Title | A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits |
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