A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits

We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using carbon nanotube field-effect transistors (CNTFETs). The circuit structure uses the body effect to mitigate the ex...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Vol. 67; no. 9; pp. 3138 - 3151
Main Authors: Kim, Sunmean, Lee, Sung-Yun, Park, Sunghye, Kim, Kyung Rok, Kang, Seokhyeong
Format: Journal Article
Language:English
Published: New York IEEE 01.09.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
body effect
Carbon nanotubes
Circuit design
Circuits
CNTFETs
Complexity theory
Energy efficiency
Field effect transistors
Gates (circuits)
Integrated circuit interconnections
Logic circuits
Logic gates
Logic synthesis
logic synthesis methodology
Methodology
Multi-valued logic
Multivalued logic
Power consumption
Semiconductor devices
ternary logic circuits
ISSN:1549-8328, 1558-0806
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using carbon nanotube field-effect transistors (CNTFETs). The circuit structure uses the body effect to mitigate the excessive power consumption for the third logic value. Energy-efficient ternary logic circuits are designed with a combination of synthesized low-power ternary logic gates. The proposed methodology is applicable to both unbalanced (0, 1, 2) and balanced (−1, 0, 1) ternary logic. To verify the improvement in energy efficiency, we have designed various ternary arithmetic logic circuits using the proposed methodology. The proposed ternary full adder has a significant improvement in the power-delay product (PDP) over previous designs. Ternary benchmark circuits have been designed to show that complex ternary functions can be designed to more efficient circuits with the proposed methodology.
Bibliography:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2020.2990748