Kim, S., Lee, S., Park, S., Kim, K. R., & Kang, S. (2020). A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits. IEEE transactions on circuits and systems. I, Regular papers, 67(9), 3138-3151. https://doi.org/10.1109/TCSI.2020.2990748
Citácia podle Chicago (17th ed.)Kim, Sunmean, Sung-Yun Lee, Sunghye Park, Kyung Rok Kim, a Seokhyeong Kang. "A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits." IEEE Transactions on Circuits and Systems. I, Regular Papers 67, no. 9 (2020): 3138-3151. https://doi.org/10.1109/TCSI.2020.2990748.
Citácia podľa MLA (8th ed.)Kim, Sunmean, et al. "A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits." IEEE Transactions on Circuits and Systems. I, Regular Papers, vol. 67, no. 9, 2020, pp. 3138-3151, https://doi.org/10.1109/TCSI.2020.2990748.