Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization

QR factorization is a ubiquitous operation in many engineering and scientific applications. In this paper, we present efficient realization of Householder Transform (HT) based QR factorization through algorithm-architecture co-design where we achieve performance improvement of 3-90x in-terms of Gflo...

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Vydáno v:	IEEE transactions on parallel and distributed systems Ročník 29; číslo 8; s. 1707 - 1720
Hlavní autoři:	Merchant, Farhad, Vatwani, Tarun, Chattopadhyay, Anupam, Raha, Soumyendu, Nandy, S. K., Narayan, Ranjani
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	New York IEEE 01.08.2018 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:	Algorithm design and analysis Algorithms Co-design Computer architecture dense linear algebra Eigenvalues and eigenfunctions Factorization Field programmable gate arrays Gate arrays Graphics processing units Householder transformations instruction level parallelism Linear algebra Microprocessors Multicore processing multiprocessor system-on-chip Parallel computing Parallel processing Software packages Transforms
ISSN:	1045-9219, 1558-2183
On-line přístup:	Získat plný text
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