Physically Unclonable and Reconfigurable Computing System (PURCS) for Hardware Security Applications

A physically unclonable and reconfigurable computing system is introduced which provides both logic locking and authentication of devices. A chaotic oscillator is required to generate the chaotic signals and can produce different Boolean functions using different tuning parameters, including a contr...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems Jg. 40; H. 3; S. 405 - 418
Hauptverfasser:	Shanta, Aysha S., Majumder, Md. Badruddoja, Hasan, Md. Sakib, Rose, Garrett S.
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.03.2021 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Aliasing Authentication Boolean Boolean algebra Boolean functions chaos chaotic map Circuits Computation computing system Gates Hardware hardware security Hybrid systems Integrated circuits Iterative methods Locking Logic circuits Logic gates logic locking Machine learning machine learning (ML) Parameters Physical unclonable function physical unclonable function (PUF) physically unclonable reconfigurable Reconfiguration SAT attack Table lookup Threshold voltage Tuning
ISSN:	0278-0070, 1937-4151
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Abstract	A physically unclonable and reconfigurable computing system is introduced which provides both logic locking and authentication of devices. A chaotic oscillator is required to generate the chaotic signals and can produce different Boolean functions using different tuning parameters, including a control bit, iteration number, threshold voltage, and bifurcation parameter. The aim of this article is to build a hybrid computing system with the mixed implementation of standard logic gates and reconfigurable chaos-based logic gates. The tuning parameters of the oscillator make up the secret key for logic locking. Process variation due to fabrication can be leveraged to generate unique keys for each chip. The whole computing system exhibits physical unclonable function (PUF) characteristics and can be used to generate challenge-response pairs (CRPs) for authenticating devices. We have used ISCAS'85 combinational benchmark circuits to demonstrate the results. The Hamming distance between correct and wrong outputs is calculated to ensure that 50% of the output bits are flipped when the wrong key is applied. A Boolean SAT attack has been carried out on the system and it displays exponential complexity with an increase in the total number of chaos gates and key size of each chaos gate. The hybrid system demonstrates near-ideal PUF metrics, including uniqueness, uniformity, and bit aliasing. Common machine learning attacks have been executed on the CRPs generated from the whole system and results show that the proposed chaos-based PUF is robust against modeling attacks. The hybrid system has significantly less overhead compared to traditional systems containing both logic locking and PUF circuitry.
AbstractList	A physically unclonable and reconfigurable computing system is introduced which provides both logic locking and authentication of devices. A chaotic oscillator is required to generate the chaotic signals and can produce different Boolean functions using different tuning parameters, including a control bit, iteration number, threshold voltage, and bifurcation parameter. The aim of this article is to build a hybrid computing system with the mixed implementation of standard logic gates and reconfigurable chaos-based logic gates. The tuning parameters of the oscillator make up the secret key for logic locking. Process variation due to fabrication can be leveraged to generate unique keys for each chip. The whole computing system exhibits physical unclonable function (PUF) characteristics and can be used to generate challenge-response pairs (CRPs) for authenticating devices. We have used ISCAS'85 combinational benchmark circuits to demonstrate the results. The Hamming distance between correct and wrong outputs is calculated to ensure that 50% of the output bits are flipped when the wrong key is applied. A Boolean SAT attack has been carried out on the system and it displays exponential complexity with an increase in the total number of chaos gates and key size of each chaos gate. The hybrid system demonstrates near-ideal PUF metrics, including uniqueness, uniformity, and bit aliasing. Common machine learning attacks have been executed on the CRPs generated from the whole system and results show that the proposed chaos-based PUF is robust against modeling attacks. The hybrid system has significantly less overhead compared to traditional systems containing both logic locking and PUF circuitry.
Author	Shanta, Aysha S. Rose, Garrett S. Majumder, Md. Badruddoja Hasan, Md. Sakib
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SubjectTerms	Aliasing Authentication Boolean Boolean algebra Boolean functions chaos chaotic map Circuits Computation computing system Gates Hardware hardware security Hybrid systems Integrated circuits Iterative methods Locking Logic circuits Logic gates logic locking Machine learning machine learning (ML) Parameters Physical unclonable function physical unclonable function (PUF) physically unclonable reconfigurable Reconfiguration SAT attack Table lookup Threshold voltage Tuning
Title	Physically Unclonable and Reconfigurable Computing System (PURCS) for Hardware Security Applications
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