Co‐design implementation of High Efficiency Video Coding standard encoder on Zynq MPSoC

Summary Statistical analysis of High Efficiency Video Coding (HEVC) encoder reveals that in the motion compensation block, the interpolation filter consumes more than 30% in the encoder time in comparison with other blocks. In this paper, we start with an optimized hardware implementation of the int...

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Bibliographic Details
Published in:International journal of circuit theory and applications Vol. 49; no. 4; pp. 1013 - 1027
Main Authors: Touzani, Hajar, Mansouri, Anass, Errahimi, Fatima, Ahaitouf, Ali
Format: Journal Article
Language:English
Published: Bognor Regis Wiley Subscription Services, Inc 01.04.2021
Subjects:
Coders
Coding
Coding standards
Field programmable gate arrays
Hardware
HEVC
HW/SW co‐design
Interpolation
interpolation filter design
Microprocessors
Motion compensation
Petalinux
Power consumption
Programmable logic arrays
Software
Statistical analysis
Video compression
Zynq SoC
ISSN:0098-9886, 1097-007X
Online Access:Get full text
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Summary:Summary Statistical analysis of High Efficiency Video Coding (HEVC) encoder reveals that in the motion compensation block, the interpolation filter consumes more than 30% in the encoder time in comparison with other blocks. In this paper, we start with an optimized hardware implementation of the interpolation filter on field‐programmable gate array (FPGA) based on Xilinx setup environment. In a second step, a Hardware/Software (HW/SW) co‐design implementation of HM16.7 encoder is performed on Zynq MPSoC platform to evaluate the proposed interpolation filter IP in terms of total encoder run‐time, taking advantages of both processing units (quad‐core ARM Cortex TM‐A53 processor and Programmable Logic FPGA component) available on the Zynq MPSoC. The proposed architecture of luma and chroma filters was simulated and synthesized on Xilinx XCZU7EV‐2FFVC1156 FPGA at 250‐MHz clock frequency. The synthesis results present an optimized power consumption of 3.308 mW for higher resolutions (2560 × 1600 and 1920 × 1080) at 50 fps with the use of just 1% of the FPGA resources. The experimental results of the co‐design implementation of HEVC encoder present a speedup of 2 times (41% in PeopleOnStreet sequence) in terms of processing time compared to the software alone implementation, with a an increase of 0.51% of bit rate and a very small degradation of peak signal‐to‐noise ratio (PSNR) (0.01%). This paper presents an optimized implementation of High Efficiency Video Coding (HEVC) on Zynq based on the co‐design technic that combines between a hardware implementation of interpolation filter on field‐programmable gate array (FPGA) and a software implementation of other blocks on ARM processor. The results present a speed‐up in encoding time of 40% compared to the full software implementation of HEVC with an increase of 0.15% on bit rate.
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ISSN:0098-9886
1097-007X
DOI:10.1002/cta.2952