Modeling and optimization of parallel disassembly line balancing problem with parallel workstations

To reasonably arrange disassembly facilities and plan enterprise space, we propose a parallel disassembly line balancing problem (PW-PDLBP) with parallel workstations. Additionally, a mixed-integer non-linear programming (MINLP) model that minimizes the line length, number of workstations, idle time...

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Bibliographic Details
Published in:IEEE transactions on industrial informatics Vol. 19; no. 11; pp. 1 - 8
Main Authors: Liang, Wei, Zhang, Zeqiang, Zeng, Yanqing, Yin, Tao, Wu, Tengfei
Format: Journal Article
Language:English
Published: Piscataway IEEE 01.11.2023
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Balancing
Dismantling
End of life
Energy consumption
Evolutionary algorithms
Evolutionary computation
Mixed integer
Mixed-integer non-linear programming
multi-objective enhanced differential evolution algorithm
Multiple objective analysis
Nonlinear programming
Optimization
parallel disassembly line balancing
parallel workstations
Workstations
ISSN:1551-3203, 1941-0050
Online Access:Get full text
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Summary:To reasonably arrange disassembly facilities and plan enterprise space, we propose a parallel disassembly line balancing problem (PW-PDLBP) with parallel workstations. Additionally, a mixed-integer non-linear programming (MINLP) model that minimizes the line length, number of workstations, idle time balancing index, and energy consumption is established based on the problem characteristics and is solved using the GUROBI optimizer. Furthermore, a multi-objective enhanced differential evolution algorithm (MEDE) is developed to obtain high-quality disassembly schemes for PW-PDLBP. The correctness of encoding and decoding and the solving performance of MEDE are verified by comparing with the MINLP model and four existing algorithms. Then, an instance consisting of two different types of end-of-life TVs is optimized. Finally, the effectiveness of PW-PDLBP in improving enterprise space utilization is validated by comparing it with the parallel line layout without parallel workstations.
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ISSN:1551-3203
1941-0050
DOI:10.1109/TII.2023.3241583